1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * David A Rusling 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2001 ARM Limited 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 7*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 8*4882a593Smuzhiyun * for more details. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef AMBA_CLCD_REGS_H 12*4882a593Smuzhiyun #define AMBA_CLCD_REGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * CLCD Controller Internal Register addresses 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define CLCD_TIM0 0x00000000 18*4882a593Smuzhiyun #define CLCD_TIM1 0x00000004 19*4882a593Smuzhiyun #define CLCD_TIM2 0x00000008 20*4882a593Smuzhiyun #define CLCD_TIM3 0x0000000c 21*4882a593Smuzhiyun #define CLCD_UBAS 0x00000010 22*4882a593Smuzhiyun #define CLCD_LBAS 0x00000014 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CLCD_PL110_IENB 0x00000018 25*4882a593Smuzhiyun #define CLCD_PL110_CNTL 0x0000001c 26*4882a593Smuzhiyun #define CLCD_PL110_STAT 0x00000020 27*4882a593Smuzhiyun #define CLCD_PL110_INTR 0x00000024 28*4882a593Smuzhiyun #define CLCD_PL110_UCUR 0x00000028 29*4882a593Smuzhiyun #define CLCD_PL110_LCUR 0x0000002C 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CLCD_PL111_CNTL 0x00000018 32*4882a593Smuzhiyun #define CLCD_PL111_IENB 0x0000001c 33*4882a593Smuzhiyun #define CLCD_PL111_RIS 0x00000020 34*4882a593Smuzhiyun #define CLCD_PL111_MIS 0x00000024 35*4882a593Smuzhiyun #define CLCD_PL111_ICR 0x00000028 36*4882a593Smuzhiyun #define CLCD_PL111_UCUR 0x0000002c 37*4882a593Smuzhiyun #define CLCD_PL111_LCUR 0x00000030 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CLCD_PALL 0x00000200 40*4882a593Smuzhiyun #define CLCD_PALETTE 0x00000200 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define TIM2_PCD_LO_MASK GENMASK(4, 0) 43*4882a593Smuzhiyun #define TIM2_PCD_LO_BITS 5 44*4882a593Smuzhiyun #define TIM2_CLKSEL (1 << 5) 45*4882a593Smuzhiyun #define TIM2_ACB_MASK GENMASK(10, 6) 46*4882a593Smuzhiyun #define TIM2_IVS (1 << 11) 47*4882a593Smuzhiyun #define TIM2_IHS (1 << 12) 48*4882a593Smuzhiyun #define TIM2_IPC (1 << 13) 49*4882a593Smuzhiyun #define TIM2_IOE (1 << 14) 50*4882a593Smuzhiyun #define TIM2_BCD (1 << 26) 51*4882a593Smuzhiyun #define TIM2_PCD_HI_MASK GENMASK(31, 27) 52*4882a593Smuzhiyun #define TIM2_PCD_HI_BITS 5 53*4882a593Smuzhiyun #define TIM2_PCD_HI_SHIFT 27 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CNTL_LCDEN (1 << 0) 56*4882a593Smuzhiyun #define CNTL_LCDBPP1 (0 << 1) 57*4882a593Smuzhiyun #define CNTL_LCDBPP2 (1 << 1) 58*4882a593Smuzhiyun #define CNTL_LCDBPP4 (2 << 1) 59*4882a593Smuzhiyun #define CNTL_LCDBPP8 (3 << 1) 60*4882a593Smuzhiyun #define CNTL_LCDBPP16 (4 << 1) 61*4882a593Smuzhiyun #define CNTL_LCDBPP16_565 (6 << 1) 62*4882a593Smuzhiyun #define CNTL_LCDBPP16_444 (7 << 1) 63*4882a593Smuzhiyun #define CNTL_LCDBPP24 (5 << 1) 64*4882a593Smuzhiyun #define CNTL_LCDBW (1 << 4) 65*4882a593Smuzhiyun #define CNTL_LCDTFT (1 << 5) 66*4882a593Smuzhiyun #define CNTL_LCDMONO8 (1 << 6) 67*4882a593Smuzhiyun #define CNTL_LCDDUAL (1 << 7) 68*4882a593Smuzhiyun #define CNTL_BGR (1 << 8) 69*4882a593Smuzhiyun #define CNTL_BEBO (1 << 9) 70*4882a593Smuzhiyun #define CNTL_BEPO (1 << 10) 71*4882a593Smuzhiyun #define CNTL_LCDPWR (1 << 11) 72*4882a593Smuzhiyun #define CNTL_LCDVCOMP(x) ((x) << 12) 73*4882a593Smuzhiyun #define CNTL_LDMAFIFOTIME (1 << 15) 74*4882a593Smuzhiyun #define CNTL_WATERMARK (1 << 16) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* ST Microelectronics variant bits */ 77*4882a593Smuzhiyun #define CNTL_ST_1XBPP_444 0x0 78*4882a593Smuzhiyun #define CNTL_ST_1XBPP_5551 (1 << 17) 79*4882a593Smuzhiyun #define CNTL_ST_1XBPP_565 (1 << 18) 80*4882a593Smuzhiyun #define CNTL_ST_CDWID_12 0x0 81*4882a593Smuzhiyun #define CNTL_ST_CDWID_16 (1 << 19) 82*4882a593Smuzhiyun #define CNTL_ST_CDWID_18 (1 << 20) 83*4882a593Smuzhiyun #define CNTL_ST_CDWID_24 ((1 << 19)|(1 << 20)) 84*4882a593Smuzhiyun #define CNTL_ST_CEAEN (1 << 21) 85*4882a593Smuzhiyun #define CNTL_ST_LCDBPP24_PACKED (6 << 1) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* AMBA_CLCD_REGS_H */ 88