1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2006 Intel Corp. 4*4882a593Smuzhiyun * Tom Long Nguyen (tom.l.nguyen@intel.com) 5*4882a593Smuzhiyun * Zhang Yanmin (yanmin.zhang@intel.com) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _AER_H_ 9*4882a593Smuzhiyun #define _AER_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/errno.h> 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define AER_NONFATAL 0 15*4882a593Smuzhiyun #define AER_FATAL 1 16*4882a593Smuzhiyun #define AER_CORRECTABLE 2 17*4882a593Smuzhiyun #define DPC_FATAL 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct pci_dev; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct aer_header_log_regs { 22*4882a593Smuzhiyun unsigned int dw0; 23*4882a593Smuzhiyun unsigned int dw1; 24*4882a593Smuzhiyun unsigned int dw2; 25*4882a593Smuzhiyun unsigned int dw3; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct aer_capability_regs { 29*4882a593Smuzhiyun u32 header; 30*4882a593Smuzhiyun u32 uncor_status; 31*4882a593Smuzhiyun u32 uncor_mask; 32*4882a593Smuzhiyun u32 uncor_severity; 33*4882a593Smuzhiyun u32 cor_status; 34*4882a593Smuzhiyun u32 cor_mask; 35*4882a593Smuzhiyun u32 cap_control; 36*4882a593Smuzhiyun struct aer_header_log_regs header_log; 37*4882a593Smuzhiyun u32 root_command; 38*4882a593Smuzhiyun u32 root_status; 39*4882a593Smuzhiyun u16 cor_err_source; 40*4882a593Smuzhiyun u16 uncor_err_source; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #if defined(CONFIG_PCIEAER) 44*4882a593Smuzhiyun /* PCIe port driver needs this function to enable AER */ 45*4882a593Smuzhiyun int pci_enable_pcie_error_reporting(struct pci_dev *dev); 46*4882a593Smuzhiyun int pci_disable_pcie_error_reporting(struct pci_dev *dev); 47*4882a593Smuzhiyun int pci_aer_clear_nonfatal_status(struct pci_dev *dev); 48*4882a593Smuzhiyun void pci_save_aer_state(struct pci_dev *dev); 49*4882a593Smuzhiyun void pci_restore_aer_state(struct pci_dev *dev); 50*4882a593Smuzhiyun #else pci_enable_pcie_error_reporting(struct pci_dev * dev)51*4882a593Smuzhiyunstatic inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) 52*4882a593Smuzhiyun { 53*4882a593Smuzhiyun return -EINVAL; 54*4882a593Smuzhiyun } pci_disable_pcie_error_reporting(struct pci_dev * dev)55*4882a593Smuzhiyunstatic inline int pci_disable_pcie_error_reporting(struct pci_dev *dev) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun return -EINVAL; 58*4882a593Smuzhiyun } pci_aer_clear_nonfatal_status(struct pci_dev * dev)59*4882a593Smuzhiyunstatic inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 60*4882a593Smuzhiyun { 61*4882a593Smuzhiyun return -EINVAL; 62*4882a593Smuzhiyun } pci_save_aer_state(struct pci_dev * dev)63*4882a593Smuzhiyunstatic inline void pci_save_aer_state(struct pci_dev *dev) {} pci_restore_aer_state(struct pci_dev * dev)64*4882a593Smuzhiyunstatic inline void pci_restore_aer_state(struct pci_dev *dev) {} 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void cper_print_aer(struct pci_dev *dev, int aer_severity, 68*4882a593Smuzhiyun struct aer_capability_regs *aer); 69*4882a593Smuzhiyun int cper_severity_to_aer(int cper_severity); 70*4882a593Smuzhiyun void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 71*4882a593Smuzhiyun int severity, struct aer_capability_regs *aer_regs); 72*4882a593Smuzhiyun #endif //_AER_H_ 73*4882a593Smuzhiyun 74