1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Google, Inc 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ADRENO_SMMU_PRIV_H 7*4882a593Smuzhiyun #define __ADRENO_SMMU_PRIV_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/io-pgtable.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /** 12*4882a593Smuzhiyun * struct adreno_smmu_priv - private interface between adreno-smmu and GPU 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * @cookie: An opque token provided by adreno-smmu and passed 15*4882a593Smuzhiyun * back into the callbacks 16*4882a593Smuzhiyun * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank 17*4882a593Smuzhiyun * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A 18*4882a593Smuzhiyun * NULL config disables TTBR0 translation, otherwise 19*4882a593Smuzhiyun * TTBR0 translation is enabled with the specified cfg 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * The GPU driver (drm/msm) and adreno-smmu work together for controlling 22*4882a593Smuzhiyun * the GPU's SMMU instance. This is by necessity, as the GPU is directly 23*4882a593Smuzhiyun * updating the SMMU for context switches, while on the other hand we do 24*4882a593Smuzhiyun * not want to duplicate all of the initial setup logic from arm-smmu. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * This private interface is used for the two drivers to coordinate. The 27*4882a593Smuzhiyun * cookie and callback functions are populated when the GPU driver attaches 28*4882a593Smuzhiyun * it's domain. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun struct adreno_smmu_priv { 31*4882a593Smuzhiyun const void *cookie; 32*4882a593Smuzhiyun const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); 33*4882a593Smuzhiyun int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __ADRENO_SMMU_PRIV_H */