1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016, Semihalf
4*4882a593Smuzhiyun * Author: Tomasz Nowicki <tn@semihalf.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __ACPI_IORT_H__
8*4882a593Smuzhiyun #define __ACPI_IORT_H__
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/acpi.h>
11*4882a593Smuzhiyun #include <linux/fwnode.h>
12*4882a593Smuzhiyun #include <linux/irqdomain.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
15*4882a593Smuzhiyun #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * PMCG model identifiers for use in smmu pmu driver. Please note
19*4882a593Smuzhiyun * that this is purely for the use of software and has nothing to
20*4882a593Smuzhiyun * do with hardware or with IORT specification.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
23*4882a593Smuzhiyun #define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun int iort_register_domain_token(int trans_id, phys_addr_t base,
26*4882a593Smuzhiyun struct fwnode_handle *fw_node);
27*4882a593Smuzhiyun void iort_deregister_domain_token(int trans_id);
28*4882a593Smuzhiyun struct fwnode_handle *iort_find_domain_token(int trans_id);
29*4882a593Smuzhiyun #ifdef CONFIG_ACPI_IORT
30*4882a593Smuzhiyun void acpi_iort_init(void);
31*4882a593Smuzhiyun u32 iort_msi_map_id(struct device *dev, u32 id);
32*4882a593Smuzhiyun struct irq_domain *iort_get_device_domain(struct device *dev, u32 id,
33*4882a593Smuzhiyun enum irq_domain_bus_token bus_token);
34*4882a593Smuzhiyun void acpi_configure_pmsi_domain(struct device *dev);
35*4882a593Smuzhiyun int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
36*4882a593Smuzhiyun /* IOMMU interface */
37*4882a593Smuzhiyun void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size);
38*4882a593Smuzhiyun const struct iommu_ops *iort_iommu_configure_id(struct device *dev,
39*4882a593Smuzhiyun const u32 *id_in);
40*4882a593Smuzhiyun int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head);
41*4882a593Smuzhiyun phys_addr_t acpi_iort_dma_get_max_cpu_address(void);
42*4882a593Smuzhiyun #else
acpi_iort_init(void)43*4882a593Smuzhiyun static inline void acpi_iort_init(void) { }
iort_msi_map_id(struct device * dev,u32 id)44*4882a593Smuzhiyun static inline u32 iort_msi_map_id(struct device *dev, u32 id)
45*4882a593Smuzhiyun { return id; }
iort_get_device_domain(struct device * dev,u32 id,enum irq_domain_bus_token bus_token)46*4882a593Smuzhiyun static inline struct irq_domain *iort_get_device_domain(
47*4882a593Smuzhiyun struct device *dev, u32 id, enum irq_domain_bus_token bus_token)
48*4882a593Smuzhiyun { return NULL; }
acpi_configure_pmsi_domain(struct device * dev)49*4882a593Smuzhiyun static inline void acpi_configure_pmsi_domain(struct device *dev) { }
50*4882a593Smuzhiyun /* IOMMU interface */
iort_dma_setup(struct device * dev,u64 * dma_addr,u64 * size)51*4882a593Smuzhiyun static inline void iort_dma_setup(struct device *dev, u64 *dma_addr,
52*4882a593Smuzhiyun u64 *size) { }
iort_iommu_configure_id(struct device * dev,const u32 * id_in)53*4882a593Smuzhiyun static inline const struct iommu_ops *iort_iommu_configure_id(
54*4882a593Smuzhiyun struct device *dev, const u32 *id_in)
55*4882a593Smuzhiyun { return NULL; }
56*4882a593Smuzhiyun static inline
iort_iommu_msi_get_resv_regions(struct device * dev,struct list_head * head)57*4882a593Smuzhiyun int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
58*4882a593Smuzhiyun { return 0; }
59*4882a593Smuzhiyun
acpi_iort_dma_get_max_cpu_address(void)60*4882a593Smuzhiyun static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void)
61*4882a593Smuzhiyun { return PHYS_ADDR_MAX; }
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #endif /* __ACPI_IORT_H__ */
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