1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_POWER_DELIVERY_H 3*4882a593Smuzhiyun #define __DT_POWER_DELIVERY_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* Power delivery Power Data Object definitions */ 6*4882a593Smuzhiyun #define PDO_TYPE_FIXED 0 7*4882a593Smuzhiyun #define PDO_TYPE_BATT 1 8*4882a593Smuzhiyun #define PDO_TYPE_VAR 2 9*4882a593Smuzhiyun #define PDO_TYPE_APDO 3 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PDO_TYPE_SHIFT 30 12*4882a593Smuzhiyun #define PDO_TYPE_MASK 0x3 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PDO_VOLT_MASK 0x3ff 17*4882a593Smuzhiyun #define PDO_CURR_MASK 0x3ff 18*4882a593Smuzhiyun #define PDO_PWR_MASK 0x3ff 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ 21*4882a593Smuzhiyun #define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ 22*4882a593Smuzhiyun #define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ 23*4882a593Smuzhiyun #define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ 24*4882a593Smuzhiyun #define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ 25*4882a593Smuzhiyun #define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ 26*4882a593Smuzhiyun #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ 27*4882a593Smuzhiyun #define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) 30*4882a593Smuzhiyun #define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PDO_FIXED(mv, ma, flags) \ 33*4882a593Smuzhiyun (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ 34*4882a593Smuzhiyun PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define VSAFE5V 5000 /* mv units */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ 39*4882a593Smuzhiyun #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ 40*4882a593Smuzhiyun #define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) 43*4882a593Smuzhiyun #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) 44*4882a593Smuzhiyun #define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define PDO_BATT(min_mv, max_mv, max_mw) \ 47*4882a593Smuzhiyun (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ 48*4882a593Smuzhiyun PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ 51*4882a593Smuzhiyun #define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ 52*4882a593Smuzhiyun #define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) 55*4882a593Smuzhiyun #define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) 56*4882a593Smuzhiyun #define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PDO_VAR(min_mv, max_mv, max_ma) \ 59*4882a593Smuzhiyun (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ 60*4882a593Smuzhiyun PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define APDO_TYPE_PPS 0 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ 65*4882a593Smuzhiyun #define PDO_APDO_TYPE_MASK 0x3 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ 70*4882a593Smuzhiyun #define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ 71*4882a593Smuzhiyun #define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define PDO_PPS_APDO_VOLT_MASK 0xff 74*4882a593Smuzhiyun #define PDO_PPS_APDO_CURR_MASK 0x7f 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define PDO_PPS_APDO_MIN_VOLT(mv) \ 77*4882a593Smuzhiyun ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) 78*4882a593Smuzhiyun #define PDO_PPS_APDO_MAX_VOLT(mv) \ 79*4882a593Smuzhiyun ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) 80*4882a593Smuzhiyun #define PDO_PPS_APDO_MAX_CURR(ma) \ 81*4882a593Smuzhiyun ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ 84*4882a593Smuzhiyun (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ 85*4882a593Smuzhiyun PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ 86*4882a593Smuzhiyun PDO_PPS_APDO_MAX_CURR(max_ma)) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Based on "Table 6-14 Fixed Supply PDO - Sink" of "USB Power Delivery Specification Revision 3.0, 90*4882a593Smuzhiyun * Version 1.2" 91*4882a593Smuzhiyun * Initial current capability of the new source when vSafe5V is applied. 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define FRS_DEFAULT_POWER 1 94*4882a593Smuzhiyun #define FRS_5V_1P5A 2 95*4882a593Smuzhiyun #define FRS_5V_3A 3 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * SVDM Identity Header 99*4882a593Smuzhiyun * -------------------- 100*4882a593Smuzhiyun * <31> :: data capable as a USB host 101*4882a593Smuzhiyun * <30> :: data capable as a USB device 102*4882a593Smuzhiyun * <29:27> :: product type (UFP / Cable / VPD) 103*4882a593Smuzhiyun * <26> :: modal operation supported (1b == yes) 104*4882a593Smuzhiyun * <25:23> :: product type (DFP) (SVDM version 2.0+ only; set to zero in version 1.0) 105*4882a593Smuzhiyun * <22:21> :: connector type (SVDM version 2.0+ only; set to zero in version 1.0) 106*4882a593Smuzhiyun * <20:16> :: Reserved, Shall be set to zero 107*4882a593Smuzhiyun * <15:0> :: USB-IF assigned VID for this cable vendor 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* PD Rev2.0 definition */ 111*4882a593Smuzhiyun #define IDH_PTYPE_UNDEF 0 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* SOP Product Type (UFP) */ 114*4882a593Smuzhiyun #define IDH_PTYPE_NOT_UFP 0 115*4882a593Smuzhiyun #define IDH_PTYPE_HUB 1 116*4882a593Smuzhiyun #define IDH_PTYPE_PERIPH 2 117*4882a593Smuzhiyun #define IDH_PTYPE_PSD 3 118*4882a593Smuzhiyun #define IDH_PTYPE_AMA 5 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* SOP' Product Type (Cable Plug / VPD) */ 121*4882a593Smuzhiyun #define IDH_PTYPE_NOT_CABLE 0 122*4882a593Smuzhiyun #define IDH_PTYPE_PCABLE 3 123*4882a593Smuzhiyun #define IDH_PTYPE_ACABLE 4 124*4882a593Smuzhiyun #define IDH_PTYPE_VPD 6 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* SOP Product Type (DFP) */ 127*4882a593Smuzhiyun #define IDH_PTYPE_NOT_DFP 0 128*4882a593Smuzhiyun #define IDH_PTYPE_DFP_HUB 1 129*4882a593Smuzhiyun #define IDH_PTYPE_DFP_HOST 2 130*4882a593Smuzhiyun #define IDH_PTYPE_DFP_PB 3 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define VDO_IDH(usbh, usbd, ufp_cable, is_modal, dfp, conn, vid) \ 133*4882a593Smuzhiyun ((usbh) << 31 | (usbd) << 30 | ((ufp_cable) & 0x7) << 27 \ 134*4882a593Smuzhiyun | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21 \ 135*4882a593Smuzhiyun | ((vid) & 0xffff)) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* 138*4882a593Smuzhiyun * Cert Stat VDO 139*4882a593Smuzhiyun * ------------- 140*4882a593Smuzhiyun * <31:0> : USB-IF assigned XID for this cable 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun #define VDO_CERT(xid) ((xid) & 0xffffffff) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* 145*4882a593Smuzhiyun * Product VDO 146*4882a593Smuzhiyun * ----------- 147*4882a593Smuzhiyun * <31:16> : USB Product ID 148*4882a593Smuzhiyun * <15:0> : USB bcdDevice 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun #define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff)) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* 153*4882a593Smuzhiyun * UFP VDO (PD Revision 3.0+ only) 154*4882a593Smuzhiyun * -------- 155*4882a593Smuzhiyun * <31:29> :: UFP VDO version 156*4882a593Smuzhiyun * <28> :: Reserved 157*4882a593Smuzhiyun * <27:24> :: Device capability 158*4882a593Smuzhiyun * <23:22> :: Connector type (10b == receptacle, 11b == captive plug) 159*4882a593Smuzhiyun * <21:11> :: Reserved 160*4882a593Smuzhiyun * <10:8> :: Vconn power (AMA only) 161*4882a593Smuzhiyun * <7> :: Vconn required (AMA only, 0b == no, 1b == yes) 162*4882a593Smuzhiyun * <6> :: Vbus required (AMA only, 0b == yes, 1b == no) 163*4882a593Smuzhiyun * <5:3> :: Alternate modes 164*4882a593Smuzhiyun * <2:0> :: USB highest speed 165*4882a593Smuzhiyun */ 166*4882a593Smuzhiyun /* UFP VDO Version */ 167*4882a593Smuzhiyun #define UFP_VDO_VER1_2 2 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Device Capability */ 170*4882a593Smuzhiyun #define DEV_USB2_CAPABLE (1 << 0) 171*4882a593Smuzhiyun #define DEV_USB2_BILLBOARD (1 << 1) 172*4882a593Smuzhiyun #define DEV_USB3_CAPABLE (1 << 2) 173*4882a593Smuzhiyun #define DEV_USB4_CAPABLE (1 << 3) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* Connector Type */ 176*4882a593Smuzhiyun #define UFP_RECEPTACLE 2 177*4882a593Smuzhiyun #define UFP_CAPTIVE 3 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* Vconn Power (AMA only, set to AMA_VCONN_NOT_REQ if Vconn is not required) */ 180*4882a593Smuzhiyun #define AMA_VCONN_PWR_1W 0 181*4882a593Smuzhiyun #define AMA_VCONN_PWR_1W5 1 182*4882a593Smuzhiyun #define AMA_VCONN_PWR_2W 2 183*4882a593Smuzhiyun #define AMA_VCONN_PWR_3W 3 184*4882a593Smuzhiyun #define AMA_VCONN_PWR_4W 4 185*4882a593Smuzhiyun #define AMA_VCONN_PWR_5W 5 186*4882a593Smuzhiyun #define AMA_VCONN_PWR_6W 6 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* Vconn Required (AMA only) */ 189*4882a593Smuzhiyun #define AMA_VCONN_NOT_REQ 0 190*4882a593Smuzhiyun #define AMA_VCONN_REQ 1 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* Vbus Required (AMA only) */ 193*4882a593Smuzhiyun #define AMA_VBUS_REQ 0 194*4882a593Smuzhiyun #define AMA_VBUS_NOT_REQ 1 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* Alternate Modes */ 197*4882a593Smuzhiyun #define UFP_ALTMODE_NOT_SUPP 0 198*4882a593Smuzhiyun #define UFP_ALTMODE_TBT3 (1 << 0) 199*4882a593Smuzhiyun #define UFP_ALTMODE_RECFG (1 << 1) 200*4882a593Smuzhiyun #define UFP_ALTMODE_NO_RECFG (1 << 2) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* USB Highest Speed */ 203*4882a593Smuzhiyun #define UFP_USB2_ONLY 0 204*4882a593Smuzhiyun #define UFP_USB32_GEN1 1 205*4882a593Smuzhiyun #define UFP_USB32_4_GEN2 2 206*4882a593Smuzhiyun #define UFP_USB4_GEN3 3 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define VDO_UFP(ver, cap, conn, vcpwr, vcr, vbr, alt, spd) \ 209*4882a593Smuzhiyun (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \ 210*4882a593Smuzhiyun | ((vcpwr) & 0x7) << 8 | (vcr) << 7 | (vbr) << 6 | ((alt) & 0x7) << 3 \ 211*4882a593Smuzhiyun | ((spd) & 0x7)) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* 214*4882a593Smuzhiyun * DFP VDO (PD Revision 3.0+ only) 215*4882a593Smuzhiyun * -------- 216*4882a593Smuzhiyun * <31:29> :: DFP VDO version 217*4882a593Smuzhiyun * <28:27> :: Reserved 218*4882a593Smuzhiyun * <26:24> :: Host capability 219*4882a593Smuzhiyun * <23:22> :: Connector type (10b == receptacle, 11b == captive plug) 220*4882a593Smuzhiyun * <21:5> :: Reserved 221*4882a593Smuzhiyun * <4:0> :: Port number 222*4882a593Smuzhiyun */ 223*4882a593Smuzhiyun #define DFP_VDO_VER1_1 1 224*4882a593Smuzhiyun #define HOST_USB2_CAPABLE (1 << 0) 225*4882a593Smuzhiyun #define HOST_USB3_CAPABLE (1 << 1) 226*4882a593Smuzhiyun #define HOST_USB4_CAPABLE (1 << 2) 227*4882a593Smuzhiyun #define DFP_RECEPTACLE 2 228*4882a593Smuzhiyun #define DFP_CAPTIVE 3 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define VDO_DFP(ver, cap, conn, pnum) \ 231*4882a593Smuzhiyun (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \ 232*4882a593Smuzhiyun | ((pnum) & 0x1f)) 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* 235*4882a593Smuzhiyun * Cable VDO (for both Passive and Active Cable VDO in PD Rev2.0) 236*4882a593Smuzhiyun * --------- 237*4882a593Smuzhiyun * <31:28> :: Cable HW version 238*4882a593Smuzhiyun * <27:24> :: Cable FW version 239*4882a593Smuzhiyun * <23:20> :: Reserved, Shall be set to zero 240*4882a593Smuzhiyun * <19:18> :: type-C to Type-A/B/C/Captive (00b == A, 01 == B, 10 == C, 11 == Captive) 241*4882a593Smuzhiyun * <17> :: Reserved, Shall be set to zero 242*4882a593Smuzhiyun * <16:13> :: cable latency (0001 == <10ns(~1m length)) 243*4882a593Smuzhiyun * <12:11> :: cable termination type (11b == both ends active VCONN req) 244*4882a593Smuzhiyun * <10> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable) 245*4882a593Smuzhiyun * <9> :: SSTX2 Directionality support 246*4882a593Smuzhiyun * <8> :: SSRX1 Directionality support 247*4882a593Smuzhiyun * <7> :: SSRX2 Directionality support 248*4882a593Smuzhiyun * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) 249*4882a593Smuzhiyun * <4> :: Vbus through cable (0b == no, 1b == yes) 250*4882a593Smuzhiyun * <3> :: SOP" controller present? (0b == no, 1b == yes) 251*4882a593Smuzhiyun * <2:0> :: USB SS Signaling support 252*4882a593Smuzhiyun * 253*4882a593Smuzhiyun * Passive Cable VDO (PD Rev3.0+) 254*4882a593Smuzhiyun * --------- 255*4882a593Smuzhiyun * <31:28> :: Cable HW version 256*4882a593Smuzhiyun * <27:24> :: Cable FW version 257*4882a593Smuzhiyun * <23:21> :: VDO version 258*4882a593Smuzhiyun * <20> :: Reserved, Shall be set to zero 259*4882a593Smuzhiyun * <19:18> :: Type-C to Type-C/Captive (10b == C, 11b == Captive) 260*4882a593Smuzhiyun * <17> :: Reserved, Shall be set to zero 261*4882a593Smuzhiyun * <16:13> :: cable latency (0001 == <10ns(~1m length)) 262*4882a593Smuzhiyun * <12:11> :: cable termination type (10b == Vconn not req, 01b == Vconn req) 263*4882a593Smuzhiyun * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) 264*4882a593Smuzhiyun * <8:7> :: Reserved, Shall be set to zero 265*4882a593Smuzhiyun * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) 266*4882a593Smuzhiyun * <4:3> :: Reserved, Shall be set to zero 267*4882a593Smuzhiyun * <2:0> :: USB highest speed 268*4882a593Smuzhiyun * 269*4882a593Smuzhiyun * Active Cable VDO 1 (PD Rev3.0+) 270*4882a593Smuzhiyun * --------- 271*4882a593Smuzhiyun * <31:28> :: Cable HW version 272*4882a593Smuzhiyun * <27:24> :: Cable FW version 273*4882a593Smuzhiyun * <23:21> :: VDO version 274*4882a593Smuzhiyun * <20> :: Reserved, Shall be set to zero 275*4882a593Smuzhiyun * <19:18> :: Connector type (10b == C, 11b == Captive) 276*4882a593Smuzhiyun * <17> :: Reserved, Shall be set to zero 277*4882a593Smuzhiyun * <16:13> :: cable latency (0001 == <10ns(~1m length)) 278*4882a593Smuzhiyun * <12:11> :: cable termination type (10b == one end active, 11b == both ends active VCONN req) 279*4882a593Smuzhiyun * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) 280*4882a593Smuzhiyun * <8> :: SBU supported (0b == supported, 1b == not supported) 281*4882a593Smuzhiyun * <7> :: SBU type (0b == passive, 1b == active) 282*4882a593Smuzhiyun * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) 283*4882a593Smuzhiyun * <4> :: Vbus through cable (0b == no, 1b == yes) 284*4882a593Smuzhiyun * <3> :: SOP" controller present? (0b == no, 1b == yes) 285*4882a593Smuzhiyun * <2:0> :: USB highest speed 286*4882a593Smuzhiyun */ 287*4882a593Smuzhiyun /* Cable VDO Version */ 288*4882a593Smuzhiyun #define CABLE_VDO_VER1_0 0 289*4882a593Smuzhiyun #define CABLE_VDO_VER1_3 3 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* Connector Type (_ATYPE and _BTYPE are for PD Rev2.0 only) */ 292*4882a593Smuzhiyun #define CABLE_ATYPE 0 293*4882a593Smuzhiyun #define CABLE_BTYPE 1 294*4882a593Smuzhiyun #define CABLE_CTYPE 2 295*4882a593Smuzhiyun #define CABLE_CAPTIVE 3 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* Cable Latency */ 298*4882a593Smuzhiyun #define CABLE_LATENCY_1M 1 299*4882a593Smuzhiyun #define CABLE_LATENCY_2M 2 300*4882a593Smuzhiyun #define CABLE_LATENCY_3M 3 301*4882a593Smuzhiyun #define CABLE_LATENCY_4M 4 302*4882a593Smuzhiyun #define CABLE_LATENCY_5M 5 303*4882a593Smuzhiyun #define CABLE_LATENCY_6M 6 304*4882a593Smuzhiyun #define CABLE_LATENCY_7M 7 305*4882a593Smuzhiyun #define CABLE_LATENCY_7M_PLUS 8 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* Cable Termination Type */ 308*4882a593Smuzhiyun #define PCABLE_VCONN_NOT_REQ 0 309*4882a593Smuzhiyun #define PCABLE_VCONN_REQ 1 310*4882a593Smuzhiyun #define ACABLE_ONE_END 2 311*4882a593Smuzhiyun #define ACABLE_BOTH_END 3 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun /* Maximum Vbus Voltage */ 314*4882a593Smuzhiyun #define CABLE_MAX_VBUS_20V 0 315*4882a593Smuzhiyun #define CABLE_MAX_VBUS_30V 1 316*4882a593Smuzhiyun #define CABLE_MAX_VBUS_40V 2 317*4882a593Smuzhiyun #define CABLE_MAX_VBUS_50V 3 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* Active Cable SBU Supported/Type */ 320*4882a593Smuzhiyun #define ACABLE_SBU_SUPP 0 321*4882a593Smuzhiyun #define ACABLE_SBU_NOT_SUPP 1 322*4882a593Smuzhiyun #define ACABLE_SBU_PASSIVE 0 323*4882a593Smuzhiyun #define ACABLE_SBU_ACTIVE 1 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun /* Vbus Current Handling Capability */ 326*4882a593Smuzhiyun #define CABLE_CURR_DEF 0 327*4882a593Smuzhiyun #define CABLE_CURR_3A 1 328*4882a593Smuzhiyun #define CABLE_CURR_5A 2 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun /* USB SuperSpeed Signaling Support (PD Rev2.0) */ 331*4882a593Smuzhiyun #define CABLE_USBSS_U2_ONLY 0 332*4882a593Smuzhiyun #define CABLE_USBSS_U31_GEN1 1 333*4882a593Smuzhiyun #define CABLE_USBSS_U31_GEN2 2 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun /* USB Highest Speed */ 336*4882a593Smuzhiyun #define CABLE_USB2_ONLY 0 337*4882a593Smuzhiyun #define CABLE_USB32_GEN1 1 338*4882a593Smuzhiyun #define CABLE_USB32_4_GEN2 2 339*4882a593Smuzhiyun #define CABLE_USB4_GEN3 3 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #define VDO_CABLE(hw, fw, cbl, lat, term, tx1d, tx2d, rx1d, rx2d, cur, vps, sopp, usbss) \ 342*4882a593Smuzhiyun (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18 \ 343*4882a593Smuzhiyun | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10 \ 344*4882a593Smuzhiyun | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5 \ 345*4882a593Smuzhiyun | (vps) << 4 | (sopp) << 3 | ((usbss) & 0x7)) 346*4882a593Smuzhiyun #define VDO_PCABLE(hw, fw, ver, conn, lat, term, vbm, cur, spd) \ 347*4882a593Smuzhiyun (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ 348*4882a593Smuzhiyun | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11 \ 349*4882a593Smuzhiyun | ((vbm) & 0x3) << 9 | ((cur) & 0x3) << 5 | ((spd) & 0x7)) 350*4882a593Smuzhiyun #define VDO_ACABLE1(hw, fw, ver, conn, lat, term, vbm, sbu, sbut, cur, vbt, sopp, spd) \ 351*4882a593Smuzhiyun (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ 352*4882a593Smuzhiyun | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11 \ 353*4882a593Smuzhiyun | ((vbm) & 0x3) << 9 | (sbu) << 8 | (sbut) << 7 | ((cur) & 0x3) << 5 \ 354*4882a593Smuzhiyun | (vbt) << 4 | (sopp) << 3 | ((spd) & 0x7)) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* 357*4882a593Smuzhiyun * Active Cable VDO 2 358*4882a593Smuzhiyun * --------- 359*4882a593Smuzhiyun * <31:24> :: Maximum operating temperature 360*4882a593Smuzhiyun * <23:16> :: Shutdown temperature 361*4882a593Smuzhiyun * <15> :: Reserved, Shall be set to zero 362*4882a593Smuzhiyun * <14:12> :: U3/CLd power 363*4882a593Smuzhiyun * <11> :: U3 to U0 transition mode (0b == direct, 1b == through U3S) 364*4882a593Smuzhiyun * <10> :: Physical connection (0b == copper, 1b == optical) 365*4882a593Smuzhiyun * <9> :: Active element (0b == redriver, 1b == retimer) 366*4882a593Smuzhiyun * <8> :: USB4 supported (0b == yes, 1b == no) 367*4882a593Smuzhiyun * <7:6> :: USB2 hub hops consumed 368*4882a593Smuzhiyun * <5> :: USB2 supported (0b == yes, 1b == no) 369*4882a593Smuzhiyun * <4> :: USB3.2 supported (0b == yes, 1b == no) 370*4882a593Smuzhiyun * <3> :: USB lanes supported (0b == one lane, 1b == two lanes) 371*4882a593Smuzhiyun * <2> :: Optically isolated active cable (0b == no, 1b == yes) 372*4882a593Smuzhiyun * <1> :: Reserved, Shall be set to zero 373*4882a593Smuzhiyun * <0> :: USB gen (0b == gen1, 1b == gen2+) 374*4882a593Smuzhiyun */ 375*4882a593Smuzhiyun /* U3/CLd Power*/ 376*4882a593Smuzhiyun #define ACAB2_U3_CLD_10MW_PLUS 0 377*4882a593Smuzhiyun #define ACAB2_U3_CLD_10MW 1 378*4882a593Smuzhiyun #define ACAB2_U3_CLD_5MW 2 379*4882a593Smuzhiyun #define ACAB2_U3_CLD_1MW 3 380*4882a593Smuzhiyun #define ACAB2_U3_CLD_500UW 4 381*4882a593Smuzhiyun #define ACAB2_U3_CLD_200UW 5 382*4882a593Smuzhiyun #define ACAB2_U3_CLD_50UW 6 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* Other Active Cable VDO 2 Fields */ 385*4882a593Smuzhiyun #define ACAB2_U3U0_DIRECT 0 386*4882a593Smuzhiyun #define ACAB2_U3U0_U3S 1 387*4882a593Smuzhiyun #define ACAB2_PHY_COPPER 0 388*4882a593Smuzhiyun #define ACAB2_PHY_OPTICAL 1 389*4882a593Smuzhiyun #define ACAB2_REDRIVER 0 390*4882a593Smuzhiyun #define ACAB2_RETIMER 1 391*4882a593Smuzhiyun #define ACAB2_USB4_SUPP 0 392*4882a593Smuzhiyun #define ACAB2_USB4_NOT_SUPP 1 393*4882a593Smuzhiyun #define ACAB2_USB2_SUPP 0 394*4882a593Smuzhiyun #define ACAB2_USB2_NOT_SUPP 1 395*4882a593Smuzhiyun #define ACAB2_USB32_SUPP 0 396*4882a593Smuzhiyun #define ACAB2_USB32_NOT_SUPP 1 397*4882a593Smuzhiyun #define ACAB2_LANES_ONE 0 398*4882a593Smuzhiyun #define ACAB2_LANES_TWO 1 399*4882a593Smuzhiyun #define ACAB2_OPT_ISO_NO 0 400*4882a593Smuzhiyun #define ACAB2_OPT_ISO_YES 1 401*4882a593Smuzhiyun #define ACAB2_GEN_1 0 402*4882a593Smuzhiyun #define ACAB2_GEN_2_PLUS 1 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \ 405*4882a593Smuzhiyun (((mtemp) & 0xff) << 24 | ((stemp) & 0xff) << 16 | ((u3p) & 0x7) << 12 \ 406*4882a593Smuzhiyun | (trans) << 11 | (phy) << 10 | (ele) << 9 | (u4) << 8 \ 407*4882a593Smuzhiyun | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \ 408*4882a593Smuzhiyun | (iso) << 2 | (gen)) 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun /* 411*4882a593Smuzhiyun * AMA VDO (PD Rev2.0) 412*4882a593Smuzhiyun * --------- 413*4882a593Smuzhiyun * <31:28> :: Cable HW version 414*4882a593Smuzhiyun * <27:24> :: Cable FW version 415*4882a593Smuzhiyun * <23:12> :: Reserved, Shall be set to zero 416*4882a593Smuzhiyun * <11> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable) 417*4882a593Smuzhiyun * <10> :: SSTX2 Directionality support 418*4882a593Smuzhiyun * <9> :: SSRX1 Directionality support 419*4882a593Smuzhiyun * <8> :: SSRX2 Directionality support 420*4882a593Smuzhiyun * <7:5> :: Vconn power 421*4882a593Smuzhiyun * <4> :: Vconn power required 422*4882a593Smuzhiyun * <3> :: Vbus power required 423*4882a593Smuzhiyun * <2:0> :: USB SS Signaling support 424*4882a593Smuzhiyun */ 425*4882a593Smuzhiyun #define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ 426*4882a593Smuzhiyun (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 \ 427*4882a593Smuzhiyun | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8 \ 428*4882a593Smuzhiyun | ((vcpwr) & 0x7) << 5 | (vcr) << 4 | (vbr) << 3 \ 429*4882a593Smuzhiyun | ((usbss) & 0x7)) 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun #define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1) 432*4882a593Smuzhiyun #define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun #define AMA_USBSS_U2_ONLY 0 435*4882a593Smuzhiyun #define AMA_USBSS_U31_GEN1 1 436*4882a593Smuzhiyun #define AMA_USBSS_U31_GEN2 2 437*4882a593Smuzhiyun #define AMA_USBSS_BBONLY 3 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun /* 440*4882a593Smuzhiyun * VPD VDO 441*4882a593Smuzhiyun * --------- 442*4882a593Smuzhiyun * <31:28> :: HW version 443*4882a593Smuzhiyun * <27:24> :: FW version 444*4882a593Smuzhiyun * <23:21> :: VDO version 445*4882a593Smuzhiyun * <20:17> :: Reserved, Shall be set to zero 446*4882a593Smuzhiyun * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) 447*4882a593Smuzhiyun * <14> :: Charge through current support (0b == 3A, 1b == 5A) 448*4882a593Smuzhiyun * <13> :: Reserved, Shall be set to zero 449*4882a593Smuzhiyun * <12:7> :: Vbus impedance 450*4882a593Smuzhiyun * <6:1> :: Ground impedance 451*4882a593Smuzhiyun * <0> :: Charge through support (0b == no, 1b == yes) 452*4882a593Smuzhiyun */ 453*4882a593Smuzhiyun #define VPD_VDO_VER1_0 0 454*4882a593Smuzhiyun #define VPD_MAX_VBUS_20V 0 455*4882a593Smuzhiyun #define VPD_MAX_VBUS_30V 1 456*4882a593Smuzhiyun #define VPD_MAX_VBUS_40V 2 457*4882a593Smuzhiyun #define VPD_MAX_VBUS_50V 3 458*4882a593Smuzhiyun #define VPDCT_CURR_3A 0 459*4882a593Smuzhiyun #define VPDCT_CURR_5A 1 460*4882a593Smuzhiyun #define VPDCT_NOT_SUPP 0 461*4882a593Smuzhiyun #define VPDCT_SUPP 1 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #define VDO_VPD(hw, fw, ver, vbm, curr, vbi, gi, ct) \ 464*4882a593Smuzhiyun (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ 465*4882a593Smuzhiyun | ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7 \ 466*4882a593Smuzhiyun | ((gi) & 0x3f) << 1 | (ct)) 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun #endif /* __DT_POWER_DELIVERY_H */ 469