1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Header providing constants for Rockchip suspend bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd 5*4882a593Smuzhiyun * Author: Power.xu 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 9*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 10*4882a593Smuzhiyun * (at your option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 13*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*4882a593Smuzhiyun * GNU General Public License for more details. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__ 19*4882a593Smuzhiyun #define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* the suspend mode */ 22*4882a593Smuzhiyun #define RKPM_CTR_PWR_DMNS (1 << 0) 23*4882a593Smuzhiyun #define RKPM_CTR_GTCLKS (1 << 1) 24*4882a593Smuzhiyun #define RKPM_CTR_PLLS (1 << 2) 25*4882a593Smuzhiyun #define RKPM_CTR_VOLTS (1 << 3) 26*4882a593Smuzhiyun #define RKPM_CTR_GPIOS (1 << 4) 27*4882a593Smuzhiyun #define RKPM_CTR_DDR (1 << 5) 28*4882a593Smuzhiyun #define RKPM_CTR_PMIC (1 << 6) 29*4882a593Smuzhiyun /* system clk is 24M,and div to min */ 30*4882a593Smuzhiyun #define RKPM_CTR_SYSCLK_DIV (1 << 7) 31*4882a593Smuzhiyun /* switch sysclk to 32k, need hardwart support, and div to min */ 32*4882a593Smuzhiyun #define RKPM_CTR_SYSCLK_32K (1 << 8) 33*4882a593Smuzhiyun /* switch sysclk to 32k,disable 24M OSC, 34*4882a593Smuzhiyun * need hardwart susport. and div to min 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define RKPM_CTR_SYSCLK_OSC_DIS (1 << 9) 37*4882a593Smuzhiyun #define RKPM_CTR_BUS_IDLE (1 << 14) 38*4882a593Smuzhiyun #define RKPM_CTR_SRAM (1 << 15) 39*4882a593Smuzhiyun /*Low Power Function Selection*/ 40*4882a593Smuzhiyun #define RKPM_CTR_IDLESRAM_MD (1 << 16) 41*4882a593Smuzhiyun #define RKPM_CTR_IDLEAUTO_MD (1 << 17) 42*4882a593Smuzhiyun #define RKPM_CTR_ARMDP_LPMD (1 << 18) 43*4882a593Smuzhiyun #define RKPM_CTR_ARMOFF_LPMD (1 << 19) 44*4882a593Smuzhiyun #define RKPM_CTR_ARMLOGDP_LPMD (1 << 20) 45*4882a593Smuzhiyun #define RKPM_CTR_ARMOFF_LOGDP_LPMD (1 << 21) 46*4882a593Smuzhiyun #define RKPM_CTR_ARMLOGOFF_DLPMD (1 << 22) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* the wake up source */ 49*4882a593Smuzhiyun #define RKPM_ARMINT_WKUP_EN (1 << 0) 50*4882a593Smuzhiyun #define RKPM_SDMMC_WKUP_EN (1 << 2) 51*4882a593Smuzhiyun #define RKPM_GPIO_WKUP_EN (1 << 3) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* the pwm regulator */ 54*4882a593Smuzhiyun #define PWM0_REGULATOR_EN (1 << 0) 55*4882a593Smuzhiyun #define PWM1_REGULATOR_EN (1 << 1) 56*4882a593Smuzhiyun #define PWM2_REGULATOR_EN (1 << 2) 57*4882a593Smuzhiyun #define PWM3_REGULATOR_EN (1 << 3) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif 60