1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Header providing constants for Rockchip suspend bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd 5*4882a593Smuzhiyun * Author: XiaoDong.Huang 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 9*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 10*4882a593Smuzhiyun * (at your option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 13*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*4882a593Smuzhiyun * GNU General Public License for more details. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ 19*4882a593Smuzhiyun #define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef BIT 22*4882a593Smuzhiyun #define BIT(nr) (1 << (nr)) 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* the suspend mode */ 26*4882a593Smuzhiyun #define RKPM_CTR_PWR_DMNS BIT(0) 27*4882a593Smuzhiyun #define RKPM_CTR_GTCLKS BIT(1) 28*4882a593Smuzhiyun #define RKPM_CTR_PLLS BIT(2) 29*4882a593Smuzhiyun #define RKPM_CTR_VOLTS BIT(3) 30*4882a593Smuzhiyun #define RKPM_CTR_GPIOS BIT(4) 31*4882a593Smuzhiyun #define RKPM_CTR_DDR BIT(5) 32*4882a593Smuzhiyun #define RKPM_CTR_PMIC BIT(6) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* system clk is 24M,and div to min */ 35*4882a593Smuzhiyun #define RKPM_CTR_SYSCLK_DIV BIT(7) 36*4882a593Smuzhiyun /* switch sysclk to 32k, need hardwart support, and div to min */ 37*4882a593Smuzhiyun #define RKPM_CTR_SYSCLK_32K BIT(8) 38*4882a593Smuzhiyun /* switch sysclk to 32k,disable 24M OSC, 39*4882a593Smuzhiyun * need hardwart susport. and div to min 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define RKPM_CTR_SYSCLK_OSC_DIS BIT(9) 42*4882a593Smuzhiyun #define RKPM_CTR_VOL_PWM0 BIT(10) 43*4882a593Smuzhiyun #define RKPM_CTR_VOL_PWM1 BIT(11) 44*4882a593Smuzhiyun #define RKPM_CTR_VOL_PWM2 BIT(12) 45*4882a593Smuzhiyun #define RKPM_CTR_VOL_PWM3 BIT(13) 46*4882a593Smuzhiyun #define RKPM_CTR_BUS_IDLE BIT(14) 47*4882a593Smuzhiyun #define RKPM_CTR_SRAM BIT(15) 48*4882a593Smuzhiyun /*Low Power Function Selection*/ 49*4882a593Smuzhiyun #define RKPM_CTR_IDLESRAM_MD BIT(16) 50*4882a593Smuzhiyun #define RKPM_CTR_IDLEAUTO_MD BIT(17) 51*4882a593Smuzhiyun #define RKPM_CTR_ARMDP_LPMD BIT(18) 52*4882a593Smuzhiyun #define RKPM_CTR_ARMOFF_LPMD BIT(19) 53*4882a593Smuzhiyun #define RKPM_CTR_ARMLOGDP_LPMD BIT(20) 54*4882a593Smuzhiyun #define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21) 55*4882a593Smuzhiyun #define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif 58