1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_RT5640_H 3*4882a593Smuzhiyun #define __DT_RT5640_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define RT5640_DMIC1_DATA_PIN_NONE 0 6*4882a593Smuzhiyun #define RT5640_DMIC1_DATA_PIN_IN1P 1 7*4882a593Smuzhiyun #define RT5640_DMIC1_DATA_PIN_GPIO3 2 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RT5640_DMIC2_DATA_PIN_NONE 0 10*4882a593Smuzhiyun #define RT5640_DMIC2_DATA_PIN_IN1N 1 11*4882a593Smuzhiyun #define RT5640_DMIC2_DATA_PIN_GPIO4 2 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define RT5640_JD_SRC_GPIO1 1 14*4882a593Smuzhiyun #define RT5640_JD_SRC_JD1_IN4P 2 15*4882a593Smuzhiyun #define RT5640_JD_SRC_JD2_IN4N 3 16*4882a593Smuzhiyun #define RT5640_JD_SRC_GPIO2 4 17*4882a593Smuzhiyun #define RT5640_JD_SRC_GPIO3 5 18*4882a593Smuzhiyun #define RT5640_JD_SRC_GPIO4 6 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define RT5640_OVCD_SF_0P5 0 21*4882a593Smuzhiyun #define RT5640_OVCD_SF_0P75 1 22*4882a593Smuzhiyun #define RT5640_OVCD_SF_1P0 2 23*4882a593Smuzhiyun #define RT5640_OVCD_SF_1P5 3 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* __DT_RT5640_H */ 26