1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_Q6_AFE_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_Q6_AFE_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* Audio Front End (AFE) virtual ports IDs */ 6*4882a593Smuzhiyun #define HDMI_RX 1 7*4882a593Smuzhiyun #define SLIMBUS_0_RX 2 8*4882a593Smuzhiyun #define SLIMBUS_0_TX 3 9*4882a593Smuzhiyun #define SLIMBUS_1_RX 4 10*4882a593Smuzhiyun #define SLIMBUS_1_TX 5 11*4882a593Smuzhiyun #define SLIMBUS_2_RX 6 12*4882a593Smuzhiyun #define SLIMBUS_2_TX 7 13*4882a593Smuzhiyun #define SLIMBUS_3_RX 8 14*4882a593Smuzhiyun #define SLIMBUS_3_TX 9 15*4882a593Smuzhiyun #define SLIMBUS_4_RX 10 16*4882a593Smuzhiyun #define SLIMBUS_4_TX 11 17*4882a593Smuzhiyun #define SLIMBUS_5_RX 12 18*4882a593Smuzhiyun #define SLIMBUS_5_TX 13 19*4882a593Smuzhiyun #define SLIMBUS_6_RX 14 20*4882a593Smuzhiyun #define SLIMBUS_6_TX 15 21*4882a593Smuzhiyun #define PRIMARY_MI2S_RX 16 22*4882a593Smuzhiyun #define PRIMARY_MI2S_TX 17 23*4882a593Smuzhiyun #define SECONDARY_MI2S_RX 18 24*4882a593Smuzhiyun #define SECONDARY_MI2S_TX 19 25*4882a593Smuzhiyun #define TERTIARY_MI2S_RX 20 26*4882a593Smuzhiyun #define TERTIARY_MI2S_TX 21 27*4882a593Smuzhiyun #define QUATERNARY_MI2S_RX 22 28*4882a593Smuzhiyun #define QUATERNARY_MI2S_TX 23 29*4882a593Smuzhiyun #define PRIMARY_TDM_RX_0 24 30*4882a593Smuzhiyun #define PRIMARY_TDM_TX_0 25 31*4882a593Smuzhiyun #define PRIMARY_TDM_RX_1 26 32*4882a593Smuzhiyun #define PRIMARY_TDM_TX_1 27 33*4882a593Smuzhiyun #define PRIMARY_TDM_RX_2 28 34*4882a593Smuzhiyun #define PRIMARY_TDM_TX_2 29 35*4882a593Smuzhiyun #define PRIMARY_TDM_RX_3 30 36*4882a593Smuzhiyun #define PRIMARY_TDM_TX_3 31 37*4882a593Smuzhiyun #define PRIMARY_TDM_RX_4 32 38*4882a593Smuzhiyun #define PRIMARY_TDM_TX_4 33 39*4882a593Smuzhiyun #define PRIMARY_TDM_RX_5 34 40*4882a593Smuzhiyun #define PRIMARY_TDM_TX_5 35 41*4882a593Smuzhiyun #define PRIMARY_TDM_RX_6 36 42*4882a593Smuzhiyun #define PRIMARY_TDM_TX_6 37 43*4882a593Smuzhiyun #define PRIMARY_TDM_RX_7 38 44*4882a593Smuzhiyun #define PRIMARY_TDM_TX_7 39 45*4882a593Smuzhiyun #define SECONDARY_TDM_RX_0 40 46*4882a593Smuzhiyun #define SECONDARY_TDM_TX_0 41 47*4882a593Smuzhiyun #define SECONDARY_TDM_RX_1 42 48*4882a593Smuzhiyun #define SECONDARY_TDM_TX_1 43 49*4882a593Smuzhiyun #define SECONDARY_TDM_RX_2 44 50*4882a593Smuzhiyun #define SECONDARY_TDM_TX_2 45 51*4882a593Smuzhiyun #define SECONDARY_TDM_RX_3 46 52*4882a593Smuzhiyun #define SECONDARY_TDM_TX_3 47 53*4882a593Smuzhiyun #define SECONDARY_TDM_RX_4 48 54*4882a593Smuzhiyun #define SECONDARY_TDM_TX_4 49 55*4882a593Smuzhiyun #define SECONDARY_TDM_RX_5 50 56*4882a593Smuzhiyun #define SECONDARY_TDM_TX_5 51 57*4882a593Smuzhiyun #define SECONDARY_TDM_RX_6 52 58*4882a593Smuzhiyun #define SECONDARY_TDM_TX_6 53 59*4882a593Smuzhiyun #define SECONDARY_TDM_RX_7 54 60*4882a593Smuzhiyun #define SECONDARY_TDM_TX_7 55 61*4882a593Smuzhiyun #define TERTIARY_TDM_RX_0 56 62*4882a593Smuzhiyun #define TERTIARY_TDM_TX_0 57 63*4882a593Smuzhiyun #define TERTIARY_TDM_RX_1 58 64*4882a593Smuzhiyun #define TERTIARY_TDM_TX_1 59 65*4882a593Smuzhiyun #define TERTIARY_TDM_RX_2 60 66*4882a593Smuzhiyun #define TERTIARY_TDM_TX_2 61 67*4882a593Smuzhiyun #define TERTIARY_TDM_RX_3 62 68*4882a593Smuzhiyun #define TERTIARY_TDM_TX_3 63 69*4882a593Smuzhiyun #define TERTIARY_TDM_RX_4 64 70*4882a593Smuzhiyun #define TERTIARY_TDM_TX_4 65 71*4882a593Smuzhiyun #define TERTIARY_TDM_RX_5 66 72*4882a593Smuzhiyun #define TERTIARY_TDM_TX_5 67 73*4882a593Smuzhiyun #define TERTIARY_TDM_RX_6 68 74*4882a593Smuzhiyun #define TERTIARY_TDM_TX_6 69 75*4882a593Smuzhiyun #define TERTIARY_TDM_RX_7 70 76*4882a593Smuzhiyun #define TERTIARY_TDM_TX_7 71 77*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_0 72 78*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_0 73 79*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_1 74 80*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_1 75 81*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_2 76 82*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_2 77 83*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_3 78 84*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_3 79 85*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_4 80 86*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_4 81 87*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_5 82 88*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_5 83 89*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_6 84 90*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_6 85 91*4882a593Smuzhiyun #define QUATERNARY_TDM_RX_7 86 92*4882a593Smuzhiyun #define QUATERNARY_TDM_TX_7 87 93*4882a593Smuzhiyun #define QUINARY_TDM_RX_0 88 94*4882a593Smuzhiyun #define QUINARY_TDM_TX_0 89 95*4882a593Smuzhiyun #define QUINARY_TDM_RX_1 90 96*4882a593Smuzhiyun #define QUINARY_TDM_TX_1 91 97*4882a593Smuzhiyun #define QUINARY_TDM_RX_2 92 98*4882a593Smuzhiyun #define QUINARY_TDM_TX_2 93 99*4882a593Smuzhiyun #define QUINARY_TDM_RX_3 94 100*4882a593Smuzhiyun #define QUINARY_TDM_TX_3 95 101*4882a593Smuzhiyun #define QUINARY_TDM_RX_4 96 102*4882a593Smuzhiyun #define QUINARY_TDM_TX_4 97 103*4882a593Smuzhiyun #define QUINARY_TDM_RX_5 98 104*4882a593Smuzhiyun #define QUINARY_TDM_TX_5 99 105*4882a593Smuzhiyun #define QUINARY_TDM_RX_6 100 106*4882a593Smuzhiyun #define QUINARY_TDM_TX_6 101 107*4882a593Smuzhiyun #define QUINARY_TDM_RX_7 102 108*4882a593Smuzhiyun #define QUINARY_TDM_TX_7 103 109*4882a593Smuzhiyun #define DISPLAY_PORT_RX 104 110*4882a593Smuzhiyun #define WSA_CODEC_DMA_RX_0 105 111*4882a593Smuzhiyun #define WSA_CODEC_DMA_TX_0 106 112*4882a593Smuzhiyun #define WSA_CODEC_DMA_RX_1 107 113*4882a593Smuzhiyun #define WSA_CODEC_DMA_TX_1 108 114*4882a593Smuzhiyun #define WSA_CODEC_DMA_TX_2 109 115*4882a593Smuzhiyun #define VA_CODEC_DMA_TX_0 110 116*4882a593Smuzhiyun #define VA_CODEC_DMA_TX_1 111 117*4882a593Smuzhiyun #define VA_CODEC_DMA_TX_2 112 118*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_0 113 119*4882a593Smuzhiyun #define TX_CODEC_DMA_TX_0 114 120*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_1 115 121*4882a593Smuzhiyun #define TX_CODEC_DMA_TX_1 116 122*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_2 117 123*4882a593Smuzhiyun #define TX_CODEC_DMA_TX_2 118 124*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_3 119 125*4882a593Smuzhiyun #define TX_CODEC_DMA_TX_3 120 126*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_4 121 127*4882a593Smuzhiyun #define TX_CODEC_DMA_TX_4 122 128*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_5 123 129*4882a593Smuzhiyun #define TX_CODEC_DMA_TX_5 124 130*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_6 125 131*4882a593Smuzhiyun #define RX_CODEC_DMA_RX_7 126 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 134*4882a593Smuzhiyun #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 135*4882a593Smuzhiyun #define LPASS_CLK_ID_SEC_MI2S_IBIT 3 136*4882a593Smuzhiyun #define LPASS_CLK_ID_SEC_MI2S_EBIT 4 137*4882a593Smuzhiyun #define LPASS_CLK_ID_TER_MI2S_IBIT 5 138*4882a593Smuzhiyun #define LPASS_CLK_ID_TER_MI2S_EBIT 6 139*4882a593Smuzhiyun #define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 140*4882a593Smuzhiyun #define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 141*4882a593Smuzhiyun #define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 142*4882a593Smuzhiyun #define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 143*4882a593Smuzhiyun #define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 144*4882a593Smuzhiyun #define LPASS_CLK_ID_QUI_MI2S_IBIT 12 145*4882a593Smuzhiyun #define LPASS_CLK_ID_QUI_MI2S_EBIT 13 146*4882a593Smuzhiyun #define LPASS_CLK_ID_SEN_MI2S_IBIT 14 147*4882a593Smuzhiyun #define LPASS_CLK_ID_SEN_MI2S_EBIT 15 148*4882a593Smuzhiyun #define LPASS_CLK_ID_INT0_MI2S_IBIT 16 149*4882a593Smuzhiyun #define LPASS_CLK_ID_INT1_MI2S_IBIT 17 150*4882a593Smuzhiyun #define LPASS_CLK_ID_INT2_MI2S_IBIT 18 151*4882a593Smuzhiyun #define LPASS_CLK_ID_INT3_MI2S_IBIT 19 152*4882a593Smuzhiyun #define LPASS_CLK_ID_INT4_MI2S_IBIT 20 153*4882a593Smuzhiyun #define LPASS_CLK_ID_INT5_MI2S_IBIT 21 154*4882a593Smuzhiyun #define LPASS_CLK_ID_INT6_MI2S_IBIT 22 155*4882a593Smuzhiyun #define LPASS_CLK_ID_QUI_MI2S_OSR 23 156*4882a593Smuzhiyun #define LPASS_CLK_ID_PRI_PCM_IBIT 24 157*4882a593Smuzhiyun #define LPASS_CLK_ID_PRI_PCM_EBIT 25 158*4882a593Smuzhiyun #define LPASS_CLK_ID_SEC_PCM_IBIT 26 159*4882a593Smuzhiyun #define LPASS_CLK_ID_SEC_PCM_EBIT 27 160*4882a593Smuzhiyun #define LPASS_CLK_ID_TER_PCM_IBIT 28 161*4882a593Smuzhiyun #define LPASS_CLK_ID_TER_PCM_EBIT 29 162*4882a593Smuzhiyun #define LPASS_CLK_ID_QUAD_PCM_IBIT 30 163*4882a593Smuzhiyun #define LPASS_CLK_ID_QUAD_PCM_EBIT 31 164*4882a593Smuzhiyun #define LPASS_CLK_ID_QUIN_PCM_IBIT 32 165*4882a593Smuzhiyun #define LPASS_CLK_ID_QUIN_PCM_EBIT 33 166*4882a593Smuzhiyun #define LPASS_CLK_ID_QUI_PCM_OSR 34 167*4882a593Smuzhiyun #define LPASS_CLK_ID_PRI_TDM_IBIT 35 168*4882a593Smuzhiyun #define LPASS_CLK_ID_PRI_TDM_EBIT 36 169*4882a593Smuzhiyun #define LPASS_CLK_ID_SEC_TDM_IBIT 37 170*4882a593Smuzhiyun #define LPASS_CLK_ID_SEC_TDM_EBIT 38 171*4882a593Smuzhiyun #define LPASS_CLK_ID_TER_TDM_IBIT 39 172*4882a593Smuzhiyun #define LPASS_CLK_ID_TER_TDM_EBIT 40 173*4882a593Smuzhiyun #define LPASS_CLK_ID_QUAD_TDM_IBIT 41 174*4882a593Smuzhiyun #define LPASS_CLK_ID_QUAD_TDM_EBIT 42 175*4882a593Smuzhiyun #define LPASS_CLK_ID_QUIN_TDM_IBIT 43 176*4882a593Smuzhiyun #define LPASS_CLK_ID_QUIN_TDM_EBIT 44 177*4882a593Smuzhiyun #define LPASS_CLK_ID_QUIN_TDM_OSR 45 178*4882a593Smuzhiyun #define LPASS_CLK_ID_MCLK_1 46 179*4882a593Smuzhiyun #define LPASS_CLK_ID_MCLK_2 47 180*4882a593Smuzhiyun #define LPASS_CLK_ID_MCLK_3 48 181*4882a593Smuzhiyun #define LPASS_CLK_ID_MCLK_4 49 182*4882a593Smuzhiyun #define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 183*4882a593Smuzhiyun #define LPASS_CLK_ID_INT_MCLK_0 51 184*4882a593Smuzhiyun #define LPASS_CLK_ID_INT_MCLK_1 52 185*4882a593Smuzhiyun #define LPASS_CLK_ID_MCLK_5 53 186*4882a593Smuzhiyun #define LPASS_CLK_ID_WSA_CORE_MCLK 54 187*4882a593Smuzhiyun #define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 188*4882a593Smuzhiyun #define LPASS_CLK_ID_VA_CORE_MCLK 56 189*4882a593Smuzhiyun #define LPASS_CLK_ID_TX_CORE_MCLK 57 190*4882a593Smuzhiyun #define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 191*4882a593Smuzhiyun #define LPASS_CLK_ID_RX_CORE_MCLK 59 192*4882a593Smuzhiyun #define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 193*4882a593Smuzhiyun #define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define LPASS_HW_AVTIMER_VOTE 101 196*4882a593Smuzhiyun #define LPASS_HW_MACRO_VOTE 102 197*4882a593Smuzhiyun #define LPASS_HW_DCODEC_VOTE 103 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define Q6AFE_MAX_CLK_ID 104 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 202*4882a593Smuzhiyun #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 203*4882a593Smuzhiyun #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 204*4882a593Smuzhiyun #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #endif /* __DT_BINDINGS_Q6_AFE_H__ */ 207