1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_FSL_IMX_AUDMUX_H 3*4882a593Smuzhiyun #define __DT_FSL_IMX_AUDMUX_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define MX27_AUDMUX_HPCR1_SSI0 0 6*4882a593Smuzhiyun #define MX27_AUDMUX_HPCR2_SSI1 1 7*4882a593Smuzhiyun #define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 8*4882a593Smuzhiyun #define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 9*4882a593Smuzhiyun #define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 10*4882a593Smuzhiyun #define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MX31_AUDMUX_PORT1_SSI0 0 13*4882a593Smuzhiyun #define MX31_AUDMUX_PORT2_SSI1 1 14*4882a593Smuzhiyun #define MX31_AUDMUX_PORT3_SSI_PINS_3 2 15*4882a593Smuzhiyun #define MX31_AUDMUX_PORT4_SSI_PINS_4 3 16*4882a593Smuzhiyun #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 17*4882a593Smuzhiyun #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 18*4882a593Smuzhiyun #define MX31_AUDMUX_PORT7_SSI_PINS_7 6 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MX51_AUDMUX_PORT1_SSI0 0 21*4882a593Smuzhiyun #define MX51_AUDMUX_PORT2_SSI1 1 22*4882a593Smuzhiyun #define MX51_AUDMUX_PORT3 2 23*4882a593Smuzhiyun #define MX51_AUDMUX_PORT4 3 24*4882a593Smuzhiyun #define MX51_AUDMUX_PORT5 4 25*4882a593Smuzhiyun #define MX51_AUDMUX_PORT6 5 26*4882a593Smuzhiyun #define MX51_AUDMUX_PORT7 6 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q) 30*4882a593Smuzhiyun * can be sourced from Rx/Tx. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define IMX_AUDMUX_RXFS 0x8 33*4882a593Smuzhiyun #define IMX_AUDMUX_RXCLK 0x8 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ 36*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) 37*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) 38*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10) 39*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_SYN (1 << 12) 40*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) 41*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) 42*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24) 43*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25) 44*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) 45*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30) 46*4882a593Smuzhiyun #define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ 49*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31) 50*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) 51*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) 52*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) 53*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21) 54*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) 55*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) 56*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) 57*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PTCR_SYN (1 << 11) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) 60*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12) 61*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) 62*4882a593Smuzhiyun #define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __DT_FSL_IMX_AUDMUX_H */ 65