1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_SOC_TEGRA_PMC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define TEGRA_PMC_CLK_OUT_1 0 10*4882a593Smuzhiyun #define TEGRA_PMC_CLK_OUT_2 1 11*4882a593Smuzhiyun #define TEGRA_PMC_CLK_OUT_3 2 12*4882a593Smuzhiyun #define TEGRA_PMC_CLK_BLINK 3 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define TEGRA_PMC_CLK_MAX 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ 17