1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2017 ROCKCHIP, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is licensed under the terms of the GNU General Public 6*4882a593Smuzhiyun * License version 2, as published by the Free Software Foundation, and 7*4882a593Smuzhiyun * may be copied, distributed, and modified under those terms. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 10*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License for more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H 17*4882a593Smuzhiyun #define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SYS_STATUS_NORMAL (1 << 0) 20*4882a593Smuzhiyun #define SYS_STATUS_SUSPEND (1 << 1) 21*4882a593Smuzhiyun #define SYS_STATUS_IDLE (1 << 2) 22*4882a593Smuzhiyun #define SYS_STATUS_REBOOT (1 << 3) 23*4882a593Smuzhiyun #define SYS_STATUS_VIDEO_4K (1 << 4) 24*4882a593Smuzhiyun #define SYS_STATUS_VIDEO_1080P (1 << 5) 25*4882a593Smuzhiyun #define SYS_STATUS_GPU (1 << 6) 26*4882a593Smuzhiyun #define SYS_STATUS_RGA (1 << 7) 27*4882a593Smuzhiyun #define SYS_STATUS_CIF0 (1 << 8) 28*4882a593Smuzhiyun #define SYS_STATUS_CIF1 (1 << 9) 29*4882a593Smuzhiyun #define SYS_STATUS_LCDC0 (1 << 10) 30*4882a593Smuzhiyun #define SYS_STATUS_LCDC1 (1 << 11) 31*4882a593Smuzhiyun #define SYS_STATUS_BOOST (1 << 12) 32*4882a593Smuzhiyun #define SYS_STATUS_PERFORMANCE (1 << 13) 33*4882a593Smuzhiyun #define SYS_STATUS_ISP (1 << 14) 34*4882a593Smuzhiyun #define SYS_STATUS_HDMI (1 << 15) 35*4882a593Smuzhiyun #define SYS_STATUS_VIDEO_4K_10B (1 << 16) 36*4882a593Smuzhiyun #define SYS_STATUS_LOW_POWER (1 << 17) 37*4882a593Smuzhiyun #define SYS_STATUS_HDMIRX (1 << 18) 38*4882a593Smuzhiyun #define SYS_STATUS_VIDEO_SVEP (1 << 19) 39*4882a593Smuzhiyun #define SYS_STATUS_VIDEO_4K_60P (1 << 20) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \ 42*4882a593Smuzhiyun SYS_STATUS_VIDEO_1080P | \ 43*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K_10B | \ 44*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K_60P) 45*4882a593Smuzhiyun #define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DMC_FREQ_LEVEL_LOW (0x1 << 0) 48*4882a593Smuzhiyun #define DMC_FREQ_LEVEL_MID_LOW (0x1 << 1) 49*4882a593Smuzhiyun #define DMC_FREQ_LEVEL_MID_HIGH (0x1 << 2) 50*4882a593Smuzhiyun #define DMC_FREQ_LEVEL_HIGH (0x1 << 3) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define DMC_WAIT_MODE_NORMAL (0x1 << 0) 53*4882a593Smuzhiyun #define DMC_WAIT_MODE_VOP_VBANK (0x1 << 1) 54*4882a593Smuzhiyun #define DMC_WAIT_MODE_VOP_LINE (0x1 << 2) 55*4882a593Smuzhiyun #define DMC_WAIT_MODE_VOP_AUTO (0x1 << 3) 56*4882a593Smuzhiyun #define DMC_WAIT_MODE_ISP_VBANK (0x1 << 4) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59