1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Xilinx, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_VERSAL_RESETS_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_VERSAL_RESETS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define VERSAL_RST_PMC_POR (0xc30c001U) 10*4882a593Smuzhiyun #define VERSAL_RST_PMC (0xc410002U) 11*4882a593Smuzhiyun #define VERSAL_RST_PS_POR (0xc30c003U) 12*4882a593Smuzhiyun #define VERSAL_RST_PL_POR (0xc30c004U) 13*4882a593Smuzhiyun #define VERSAL_RST_NOC_POR (0xc30c005U) 14*4882a593Smuzhiyun #define VERSAL_RST_FPD_POR (0xc30c006U) 15*4882a593Smuzhiyun #define VERSAL_RST_ACPU_0_POR (0xc30c007U) 16*4882a593Smuzhiyun #define VERSAL_RST_ACPU_1_POR (0xc30c008U) 17*4882a593Smuzhiyun #define VERSAL_RST_OCM2_POR (0xc30c009U) 18*4882a593Smuzhiyun #define VERSAL_RST_PS_SRST (0xc41000aU) 19*4882a593Smuzhiyun #define VERSAL_RST_PL_SRST (0xc41000bU) 20*4882a593Smuzhiyun #define VERSAL_RST_NOC (0xc41000cU) 21*4882a593Smuzhiyun #define VERSAL_RST_NPI (0xc41000dU) 22*4882a593Smuzhiyun #define VERSAL_RST_SYS_RST_1 (0xc41000eU) 23*4882a593Smuzhiyun #define VERSAL_RST_SYS_RST_2 (0xc41000fU) 24*4882a593Smuzhiyun #define VERSAL_RST_SYS_RST_3 (0xc410010U) 25*4882a593Smuzhiyun #define VERSAL_RST_FPD (0xc410011U) 26*4882a593Smuzhiyun #define VERSAL_RST_PL0 (0xc410012U) 27*4882a593Smuzhiyun #define VERSAL_RST_PL1 (0xc410013U) 28*4882a593Smuzhiyun #define VERSAL_RST_PL2 (0xc410014U) 29*4882a593Smuzhiyun #define VERSAL_RST_PL3 (0xc410015U) 30*4882a593Smuzhiyun #define VERSAL_RST_APU (0xc410016U) 31*4882a593Smuzhiyun #define VERSAL_RST_ACPU_0 (0xc410017U) 32*4882a593Smuzhiyun #define VERSAL_RST_ACPU_1 (0xc410018U) 33*4882a593Smuzhiyun #define VERSAL_RST_ACPU_L2 (0xc410019U) 34*4882a593Smuzhiyun #define VERSAL_RST_ACPU_GIC (0xc41001aU) 35*4882a593Smuzhiyun #define VERSAL_RST_RPU_ISLAND (0xc41001bU) 36*4882a593Smuzhiyun #define VERSAL_RST_RPU_AMBA (0xc41001cU) 37*4882a593Smuzhiyun #define VERSAL_RST_R5_0 (0xc41001dU) 38*4882a593Smuzhiyun #define VERSAL_RST_R5_1 (0xc41001eU) 39*4882a593Smuzhiyun #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) 40*4882a593Smuzhiyun #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) 41*4882a593Smuzhiyun #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) 42*4882a593Smuzhiyun #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) 43*4882a593Smuzhiyun #define VERSAL_RST_SYSMON_LPD (0xc410023U) 44*4882a593Smuzhiyun #define VERSAL_RST_PDMA_RST1 (0xc410024U) 45*4882a593Smuzhiyun #define VERSAL_RST_PDMA_RST0 (0xc410025U) 46*4882a593Smuzhiyun #define VERSAL_RST_ADMA (0xc410026U) 47*4882a593Smuzhiyun #define VERSAL_RST_TIMESTAMP (0xc410027U) 48*4882a593Smuzhiyun #define VERSAL_RST_OCM (0xc410028U) 49*4882a593Smuzhiyun #define VERSAL_RST_OCM2_RST (0xc410029U) 50*4882a593Smuzhiyun #define VERSAL_RST_IPI (0xc41002aU) 51*4882a593Smuzhiyun #define VERSAL_RST_SBI (0xc41002bU) 52*4882a593Smuzhiyun #define VERSAL_RST_LPD (0xc41002cU) 53*4882a593Smuzhiyun #define VERSAL_RST_QSPI (0xc10402dU) 54*4882a593Smuzhiyun #define VERSAL_RST_OSPI (0xc10402eU) 55*4882a593Smuzhiyun #define VERSAL_RST_SDIO_0 (0xc10402fU) 56*4882a593Smuzhiyun #define VERSAL_RST_SDIO_1 (0xc104030U) 57*4882a593Smuzhiyun #define VERSAL_RST_I2C_PMC (0xc104031U) 58*4882a593Smuzhiyun #define VERSAL_RST_GPIO_PMC (0xc104032U) 59*4882a593Smuzhiyun #define VERSAL_RST_GEM_0 (0xc104033U) 60*4882a593Smuzhiyun #define VERSAL_RST_GEM_1 (0xc104034U) 61*4882a593Smuzhiyun #define VERSAL_RST_SPARE (0xc104035U) 62*4882a593Smuzhiyun #define VERSAL_RST_USB_0 (0xc104036U) 63*4882a593Smuzhiyun #define VERSAL_RST_UART_0 (0xc104037U) 64*4882a593Smuzhiyun #define VERSAL_RST_UART_1 (0xc104038U) 65*4882a593Smuzhiyun #define VERSAL_RST_SPI_0 (0xc104039U) 66*4882a593Smuzhiyun #define VERSAL_RST_SPI_1 (0xc10403aU) 67*4882a593Smuzhiyun #define VERSAL_RST_CAN_FD_0 (0xc10403bU) 68*4882a593Smuzhiyun #define VERSAL_RST_CAN_FD_1 (0xc10403cU) 69*4882a593Smuzhiyun #define VERSAL_RST_I2C_0 (0xc10403dU) 70*4882a593Smuzhiyun #define VERSAL_RST_I2C_1 (0xc10403eU) 71*4882a593Smuzhiyun #define VERSAL_RST_GPIO_LPD (0xc10403fU) 72*4882a593Smuzhiyun #define VERSAL_RST_TTC_0 (0xc104040U) 73*4882a593Smuzhiyun #define VERSAL_RST_TTC_1 (0xc104041U) 74*4882a593Smuzhiyun #define VERSAL_RST_TTC_2 (0xc104042U) 75*4882a593Smuzhiyun #define VERSAL_RST_TTC_3 (0xc104043U) 76*4882a593Smuzhiyun #define VERSAL_RST_SWDT_FPD (0xc104044U) 77*4882a593Smuzhiyun #define VERSAL_RST_SWDT_LPD (0xc104045U) 78*4882a593Smuzhiyun #define VERSAL_RST_USB (0xc104046U) 79*4882a593Smuzhiyun #define VERSAL_RST_DPC (0xc208047U) 80*4882a593Smuzhiyun #define VERSAL_RST_PMCDBG (0xc208048U) 81*4882a593Smuzhiyun #define VERSAL_RST_DBG_TRACE (0xc208049U) 82*4882a593Smuzhiyun #define VERSAL_RST_DBG_FPD (0xc20804aU) 83*4882a593Smuzhiyun #define VERSAL_RST_DBG_TSTMP (0xc20804bU) 84*4882a593Smuzhiyun #define VERSAL_RST_RPU0_DBG (0xc20804cU) 85*4882a593Smuzhiyun #define VERSAL_RST_RPU1_DBG (0xc20804dU) 86*4882a593Smuzhiyun #define VERSAL_RST_HSDP (0xc20804eU) 87*4882a593Smuzhiyun #define VERSAL_RST_DBG_LPD (0xc20804fU) 88*4882a593Smuzhiyun #define VERSAL_RST_CPM_POR (0xc30c050U) 89*4882a593Smuzhiyun #define VERSAL_RST_CPM (0xc410051U) 90*4882a593Smuzhiyun #define VERSAL_RST_CPMDBG (0xc208052U) 91*4882a593Smuzhiyun #define VERSAL_RST_PCIE_CFG (0xc410053U) 92*4882a593Smuzhiyun #define VERSAL_RST_PCIE_CORE0 (0xc410054U) 93*4882a593Smuzhiyun #define VERSAL_RST_PCIE_CORE1 (0xc410055U) 94*4882a593Smuzhiyun #define VERSAL_RST_PCIE_DMA (0xc410056U) 95*4882a593Smuzhiyun #define VERSAL_RST_CMN (0xc410057U) 96*4882a593Smuzhiyun #define VERSAL_RST_L2_0 (0xc410058U) 97*4882a593Smuzhiyun #define VERSAL_RST_L2_1 (0xc410059U) 98*4882a593Smuzhiyun #define VERSAL_RST_ADDR_REMAP (0xc41005aU) 99*4882a593Smuzhiyun #define VERSAL_RST_CPI0 (0xc41005bU) 100*4882a593Smuzhiyun #define VERSAL_RST_CPI1 (0xc41005cU) 101*4882a593Smuzhiyun #define VERSAL_RST_XRAM (0xc30c05dU) 102*4882a593Smuzhiyun #define VERSAL_RST_AIE_ARRAY (0xc10405eU) 103*4882a593Smuzhiyun #define VERSAL_RST_AIE_SHIM (0xc10405fU) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif 106