1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ 8*4882a593Smuzhiyun #define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define RST_USB_PHY0 0 11*4882a593Smuzhiyun #define RST_BUS_DMA 1 12*4882a593Smuzhiyun #define RST_BUS_MMC0 2 13*4882a593Smuzhiyun #define RST_BUS_MMC1 3 14*4882a593Smuzhiyun #define RST_BUS_DRAM 4 15*4882a593Smuzhiyun #define RST_BUS_SPI0 5 16*4882a593Smuzhiyun #define RST_BUS_SPI1 6 17*4882a593Smuzhiyun #define RST_BUS_OTG 7 18*4882a593Smuzhiyun #define RST_BUS_VE 8 19*4882a593Smuzhiyun #define RST_BUS_LCD 9 20*4882a593Smuzhiyun #define RST_BUS_DEINTERLACE 10 21*4882a593Smuzhiyun #define RST_BUS_CSI 11 22*4882a593Smuzhiyun #define RST_BUS_TVD 12 23*4882a593Smuzhiyun #define RST_BUS_TVE 13 24*4882a593Smuzhiyun #define RST_BUS_DE_BE 14 25*4882a593Smuzhiyun #define RST_BUS_DE_FE 15 26*4882a593Smuzhiyun #define RST_BUS_CODEC 16 27*4882a593Smuzhiyun #define RST_BUS_SPDIF 17 28*4882a593Smuzhiyun #define RST_BUS_IR 18 29*4882a593Smuzhiyun #define RST_BUS_RSB 19 30*4882a593Smuzhiyun #define RST_BUS_I2S0 20 31*4882a593Smuzhiyun #define RST_BUS_I2C0 21 32*4882a593Smuzhiyun #define RST_BUS_I2C1 22 33*4882a593Smuzhiyun #define RST_BUS_I2C2 23 34*4882a593Smuzhiyun #define RST_BUS_UART0 24 35*4882a593Smuzhiyun #define RST_BUS_UART1 25 36*4882a593Smuzhiyun #define RST_BUS_UART2 26 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ 39