1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_SUN50I_H6_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RST_MBUS 0 10*4882a593Smuzhiyun #define RST_BUS_DE 1 11*4882a593Smuzhiyun #define RST_BUS_DEINTERLACE 2 12*4882a593Smuzhiyun #define RST_BUS_GPU 3 13*4882a593Smuzhiyun #define RST_BUS_CE 4 14*4882a593Smuzhiyun #define RST_BUS_VE 5 15*4882a593Smuzhiyun #define RST_BUS_EMCE 6 16*4882a593Smuzhiyun #define RST_BUS_VP9 7 17*4882a593Smuzhiyun #define RST_BUS_DMA 8 18*4882a593Smuzhiyun #define RST_BUS_MSGBOX 9 19*4882a593Smuzhiyun #define RST_BUS_SPINLOCK 10 20*4882a593Smuzhiyun #define RST_BUS_HSTIMER 11 21*4882a593Smuzhiyun #define RST_BUS_DBG 12 22*4882a593Smuzhiyun #define RST_BUS_PSI 13 23*4882a593Smuzhiyun #define RST_BUS_PWM 14 24*4882a593Smuzhiyun #define RST_BUS_IOMMU 15 25*4882a593Smuzhiyun #define RST_BUS_DRAM 16 26*4882a593Smuzhiyun #define RST_BUS_NAND 17 27*4882a593Smuzhiyun #define RST_BUS_MMC0 18 28*4882a593Smuzhiyun #define RST_BUS_MMC1 19 29*4882a593Smuzhiyun #define RST_BUS_MMC2 20 30*4882a593Smuzhiyun #define RST_BUS_UART0 21 31*4882a593Smuzhiyun #define RST_BUS_UART1 22 32*4882a593Smuzhiyun #define RST_BUS_UART2 23 33*4882a593Smuzhiyun #define RST_BUS_UART3 24 34*4882a593Smuzhiyun #define RST_BUS_I2C0 25 35*4882a593Smuzhiyun #define RST_BUS_I2C1 26 36*4882a593Smuzhiyun #define RST_BUS_I2C2 27 37*4882a593Smuzhiyun #define RST_BUS_I2C3 28 38*4882a593Smuzhiyun #define RST_BUS_SCR0 29 39*4882a593Smuzhiyun #define RST_BUS_SCR1 30 40*4882a593Smuzhiyun #define RST_BUS_SPI0 31 41*4882a593Smuzhiyun #define RST_BUS_SPI1 32 42*4882a593Smuzhiyun #define RST_BUS_EMAC 33 43*4882a593Smuzhiyun #define RST_BUS_TS 34 44*4882a593Smuzhiyun #define RST_BUS_IR_TX 35 45*4882a593Smuzhiyun #define RST_BUS_THS 36 46*4882a593Smuzhiyun #define RST_BUS_I2S0 37 47*4882a593Smuzhiyun #define RST_BUS_I2S1 38 48*4882a593Smuzhiyun #define RST_BUS_I2S2 39 49*4882a593Smuzhiyun #define RST_BUS_I2S3 40 50*4882a593Smuzhiyun #define RST_BUS_SPDIF 41 51*4882a593Smuzhiyun #define RST_BUS_DMIC 42 52*4882a593Smuzhiyun #define RST_BUS_AUDIO_HUB 43 53*4882a593Smuzhiyun #define RST_USB_PHY0 44 54*4882a593Smuzhiyun #define RST_USB_PHY1 45 55*4882a593Smuzhiyun #define RST_USB_PHY3 46 56*4882a593Smuzhiyun #define RST_USB_HSIC 47 57*4882a593Smuzhiyun #define RST_BUS_OHCI0 48 58*4882a593Smuzhiyun #define RST_BUS_OHCI3 49 59*4882a593Smuzhiyun #define RST_BUS_EHCI0 50 60*4882a593Smuzhiyun #define RST_BUS_XHCI 51 61*4882a593Smuzhiyun #define RST_BUS_EHCI3 52 62*4882a593Smuzhiyun #define RST_BUS_OTG 53 63*4882a593Smuzhiyun #define RST_BUS_PCIE 54 64*4882a593Smuzhiyun #define RST_PCIE_POWERUP 55 65*4882a593Smuzhiyun #define RST_BUS_HDMI 56 66*4882a593Smuzhiyun #define RST_BUS_HDMI_SUB 57 67*4882a593Smuzhiyun #define RST_BUS_TCON_TOP 58 68*4882a593Smuzhiyun #define RST_BUS_TCON_LCD0 59 69*4882a593Smuzhiyun #define RST_BUS_TCON_TV0 60 70*4882a593Smuzhiyun #define RST_BUS_CSI 61 71*4882a593Smuzhiyun #define RST_BUS_HDCP 62 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ 74