1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_SUN50I_A100_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RST_MBUS 0 10*4882a593Smuzhiyun #define RST_BUS_DE 1 11*4882a593Smuzhiyun #define RST_BUS_G2D 2 12*4882a593Smuzhiyun #define RST_BUS_GPU 3 13*4882a593Smuzhiyun #define RST_BUS_CE 4 14*4882a593Smuzhiyun #define RST_BUS_VE 5 15*4882a593Smuzhiyun #define RST_BUS_DMA 6 16*4882a593Smuzhiyun #define RST_BUS_MSGBOX 7 17*4882a593Smuzhiyun #define RST_BUS_SPINLOCK 8 18*4882a593Smuzhiyun #define RST_BUS_HSTIMER 9 19*4882a593Smuzhiyun #define RST_BUS_DBG 10 20*4882a593Smuzhiyun #define RST_BUS_PSI 11 21*4882a593Smuzhiyun #define RST_BUS_PWM 12 22*4882a593Smuzhiyun #define RST_BUS_DRAM 13 23*4882a593Smuzhiyun #define RST_BUS_NAND 14 24*4882a593Smuzhiyun #define RST_BUS_MMC0 15 25*4882a593Smuzhiyun #define RST_BUS_MMC1 16 26*4882a593Smuzhiyun #define RST_BUS_MMC2 17 27*4882a593Smuzhiyun #define RST_BUS_UART0 18 28*4882a593Smuzhiyun #define RST_BUS_UART1 19 29*4882a593Smuzhiyun #define RST_BUS_UART2 20 30*4882a593Smuzhiyun #define RST_BUS_UART3 21 31*4882a593Smuzhiyun #define RST_BUS_UART4 22 32*4882a593Smuzhiyun #define RST_BUS_I2C0 23 33*4882a593Smuzhiyun #define RST_BUS_I2C1 24 34*4882a593Smuzhiyun #define RST_BUS_I2C2 25 35*4882a593Smuzhiyun #define RST_BUS_I2C3 26 36*4882a593Smuzhiyun #define RST_BUS_SPI0 27 37*4882a593Smuzhiyun #define RST_BUS_SPI1 28 38*4882a593Smuzhiyun #define RST_BUS_SPI2 29 39*4882a593Smuzhiyun #define RST_BUS_EMAC 30 40*4882a593Smuzhiyun #define RST_BUS_IR_RX 31 41*4882a593Smuzhiyun #define RST_BUS_IR_TX 32 42*4882a593Smuzhiyun #define RST_BUS_GPADC 33 43*4882a593Smuzhiyun #define RST_BUS_THS 34 44*4882a593Smuzhiyun #define RST_BUS_I2S0 35 45*4882a593Smuzhiyun #define RST_BUS_I2S1 36 46*4882a593Smuzhiyun #define RST_BUS_I2S2 37 47*4882a593Smuzhiyun #define RST_BUS_I2S3 38 48*4882a593Smuzhiyun #define RST_BUS_SPDIF 39 49*4882a593Smuzhiyun #define RST_BUS_DMIC 40 50*4882a593Smuzhiyun #define RST_BUS_AUDIO_CODEC 41 51*4882a593Smuzhiyun #define RST_USB_PHY0 42 52*4882a593Smuzhiyun #define RST_USB_PHY1 43 53*4882a593Smuzhiyun #define RST_BUS_OHCI0 44 54*4882a593Smuzhiyun #define RST_BUS_OHCI1 45 55*4882a593Smuzhiyun #define RST_BUS_EHCI0 46 56*4882a593Smuzhiyun #define RST_BUS_EHCI1 47 57*4882a593Smuzhiyun #define RST_BUS_OTG 48 58*4882a593Smuzhiyun #define RST_BUS_LRADC 49 59*4882a593Smuzhiyun #define RST_BUS_DPSS_TOP0 50 60*4882a593Smuzhiyun #define RST_BUS_DPSS_TOP1 51 61*4882a593Smuzhiyun #define RST_BUS_MIPI_DSI 52 62*4882a593Smuzhiyun #define RST_BUS_TCON_LCD 53 63*4882a593Smuzhiyun #define RST_BUS_LVDS 54 64*4882a593Smuzhiyun #define RST_BUS_LEDC 55 65*4882a593Smuzhiyun #define RST_BUS_CSI 56 66*4882a593Smuzhiyun #define RST_BUS_CSI_ISP 57 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */ 69