1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4*4882a593Smuzhiyun * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ 8*4882a593Smuzhiyun #define _DT_BINDINGS_STM32MP1_RESET_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define LTDC_R 3072 11*4882a593Smuzhiyun #define DSI_R 3076 12*4882a593Smuzhiyun #define DDRPERFM_R 3080 13*4882a593Smuzhiyun #define USBPHY_R 3088 14*4882a593Smuzhiyun #define SPI6_R 3136 15*4882a593Smuzhiyun #define I2C4_R 3138 16*4882a593Smuzhiyun #define I2C6_R 3139 17*4882a593Smuzhiyun #define USART1_R 3140 18*4882a593Smuzhiyun #define STGEN_R 3156 19*4882a593Smuzhiyun #define GPIOZ_R 3200 20*4882a593Smuzhiyun #define CRYP1_R 3204 21*4882a593Smuzhiyun #define HASH1_R 3205 22*4882a593Smuzhiyun #define RNG1_R 3206 23*4882a593Smuzhiyun #define AXIM_R 3216 24*4882a593Smuzhiyun #define GPU_R 3269 25*4882a593Smuzhiyun #define ETHMAC_R 3274 26*4882a593Smuzhiyun #define FMC_R 3276 27*4882a593Smuzhiyun #define QSPI_R 3278 28*4882a593Smuzhiyun #define SDMMC1_R 3280 29*4882a593Smuzhiyun #define SDMMC2_R 3281 30*4882a593Smuzhiyun #define CRC1_R 3284 31*4882a593Smuzhiyun #define USBH_R 3288 32*4882a593Smuzhiyun #define MDMA_R 3328 33*4882a593Smuzhiyun #define MCU_R 8225 34*4882a593Smuzhiyun #define TIM2_R 19456 35*4882a593Smuzhiyun #define TIM3_R 19457 36*4882a593Smuzhiyun #define TIM4_R 19458 37*4882a593Smuzhiyun #define TIM5_R 19459 38*4882a593Smuzhiyun #define TIM6_R 19460 39*4882a593Smuzhiyun #define TIM7_R 19461 40*4882a593Smuzhiyun #define TIM12_R 16462 41*4882a593Smuzhiyun #define TIM13_R 16463 42*4882a593Smuzhiyun #define TIM14_R 16464 43*4882a593Smuzhiyun #define LPTIM1_R 19465 44*4882a593Smuzhiyun #define SPI2_R 19467 45*4882a593Smuzhiyun #define SPI3_R 19468 46*4882a593Smuzhiyun #define USART2_R 19470 47*4882a593Smuzhiyun #define USART3_R 19471 48*4882a593Smuzhiyun #define UART4_R 19472 49*4882a593Smuzhiyun #define UART5_R 19473 50*4882a593Smuzhiyun #define UART7_R 19474 51*4882a593Smuzhiyun #define UART8_R 19475 52*4882a593Smuzhiyun #define I2C1_R 19477 53*4882a593Smuzhiyun #define I2C2_R 19478 54*4882a593Smuzhiyun #define I2C3_R 19479 55*4882a593Smuzhiyun #define I2C5_R 19480 56*4882a593Smuzhiyun #define SPDIF_R 19482 57*4882a593Smuzhiyun #define CEC_R 19483 58*4882a593Smuzhiyun #define DAC12_R 19485 59*4882a593Smuzhiyun #define MDIO_R 19847 60*4882a593Smuzhiyun #define TIM1_R 19520 61*4882a593Smuzhiyun #define TIM8_R 19521 62*4882a593Smuzhiyun #define TIM15_R 19522 63*4882a593Smuzhiyun #define TIM16_R 19523 64*4882a593Smuzhiyun #define TIM17_R 19524 65*4882a593Smuzhiyun #define SPI1_R 19528 66*4882a593Smuzhiyun #define SPI4_R 19529 67*4882a593Smuzhiyun #define SPI5_R 19530 68*4882a593Smuzhiyun #define USART6_R 19533 69*4882a593Smuzhiyun #define SAI1_R 19536 70*4882a593Smuzhiyun #define SAI2_R 19537 71*4882a593Smuzhiyun #define SAI3_R 19538 72*4882a593Smuzhiyun #define DFSDM_R 19540 73*4882a593Smuzhiyun #define FDCAN_R 19544 74*4882a593Smuzhiyun #define LPTIM2_R 19584 75*4882a593Smuzhiyun #define LPTIM3_R 19585 76*4882a593Smuzhiyun #define LPTIM4_R 19586 77*4882a593Smuzhiyun #define LPTIM5_R 19587 78*4882a593Smuzhiyun #define SAI4_R 19592 79*4882a593Smuzhiyun #define SYSCFG_R 19595 80*4882a593Smuzhiyun #define VREF_R 19597 81*4882a593Smuzhiyun #define TMPSENS_R 19600 82*4882a593Smuzhiyun #define PMBCTRL_R 19601 83*4882a593Smuzhiyun #define DMA1_R 19648 84*4882a593Smuzhiyun #define DMA2_R 19649 85*4882a593Smuzhiyun #define DMAMUX_R 19650 86*4882a593Smuzhiyun #define ADC12_R 19653 87*4882a593Smuzhiyun #define USBO_R 19656 88*4882a593Smuzhiyun #define SDMMC3_R 19664 89*4882a593Smuzhiyun #define CAMITF_R 19712 90*4882a593Smuzhiyun #define CRYP2_R 19716 91*4882a593Smuzhiyun #define HASH2_R 19717 92*4882a593Smuzhiyun #define RNG2_R 19718 93*4882a593Smuzhiyun #define CRC2_R 19719 94*4882a593Smuzhiyun #define HSEM_R 19723 95*4882a593Smuzhiyun #define MBOX_R 19724 96*4882a593Smuzhiyun #define GPIOA_R 19776 97*4882a593Smuzhiyun #define GPIOB_R 19777 98*4882a593Smuzhiyun #define GPIOC_R 19778 99*4882a593Smuzhiyun #define GPIOD_R 19779 100*4882a593Smuzhiyun #define GPIOE_R 19780 101*4882a593Smuzhiyun #define GPIOF_R 19781 102*4882a593Smuzhiyun #define GPIOG_R 19782 103*4882a593Smuzhiyun #define GPIOH_R 19783 104*4882a593Smuzhiyun #define GPIOI_R 19784 105*4882a593Smuzhiyun #define GPIOJ_R 19785 106*4882a593Smuzhiyun #define GPIOK_R 19786 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ 109