1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for the reset controller 4*4882a593Smuzhiyun * based peripheral powerdown requests on the STMicroelectronics 5*4882a593Smuzhiyun * STiH407 SoC. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 8*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_STIH407 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Powerdown requests control 0 */ 11*4882a593Smuzhiyun #define STIH407_EMISS_POWERDOWN 0 12*4882a593Smuzhiyun #define STIH407_NAND_POWERDOWN 1 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Synp GMAC PowerDown */ 15*4882a593Smuzhiyun #define STIH407_ETH1_POWERDOWN 2 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Powerdown requests control 1 */ 18*4882a593Smuzhiyun #define STIH407_USB3_POWERDOWN 3 19*4882a593Smuzhiyun #define STIH407_USB2_PORT1_POWERDOWN 4 20*4882a593Smuzhiyun #define STIH407_USB2_PORT0_POWERDOWN 5 21*4882a593Smuzhiyun #define STIH407_PCIE1_POWERDOWN 6 22*4882a593Smuzhiyun #define STIH407_PCIE0_POWERDOWN 7 23*4882a593Smuzhiyun #define STIH407_SATA1_POWERDOWN 8 24*4882a593Smuzhiyun #define STIH407_SATA0_POWERDOWN 9 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Reset defines */ 27*4882a593Smuzhiyun #define STIH407_ETH1_SOFTRESET 0 28*4882a593Smuzhiyun #define STIH407_MMC1_SOFTRESET 1 29*4882a593Smuzhiyun #define STIH407_PICOPHY_SOFTRESET 2 30*4882a593Smuzhiyun #define STIH407_IRB_SOFTRESET 3 31*4882a593Smuzhiyun #define STIH407_PCIE0_SOFTRESET 4 32*4882a593Smuzhiyun #define STIH407_PCIE1_SOFTRESET 5 33*4882a593Smuzhiyun #define STIH407_SATA0_SOFTRESET 6 34*4882a593Smuzhiyun #define STIH407_SATA1_SOFTRESET 7 35*4882a593Smuzhiyun #define STIH407_MIPHY0_SOFTRESET 8 36*4882a593Smuzhiyun #define STIH407_MIPHY1_SOFTRESET 9 37*4882a593Smuzhiyun #define STIH407_MIPHY2_SOFTRESET 10 38*4882a593Smuzhiyun #define STIH407_SATA0_PWR_SOFTRESET 11 39*4882a593Smuzhiyun #define STIH407_SATA1_PWR_SOFTRESET 12 40*4882a593Smuzhiyun #define STIH407_DELTA_SOFTRESET 13 41*4882a593Smuzhiyun #define STIH407_BLITTER_SOFTRESET 14 42*4882a593Smuzhiyun #define STIH407_HDTVOUT_SOFTRESET 15 43*4882a593Smuzhiyun #define STIH407_HDQVDP_SOFTRESET 16 44*4882a593Smuzhiyun #define STIH407_VDP_AUX_SOFTRESET 17 45*4882a593Smuzhiyun #define STIH407_COMPO_SOFTRESET 18 46*4882a593Smuzhiyun #define STIH407_HDMI_TX_PHY_SOFTRESET 19 47*4882a593Smuzhiyun #define STIH407_JPEG_DEC_SOFTRESET 20 48*4882a593Smuzhiyun #define STIH407_VP8_DEC_SOFTRESET 21 49*4882a593Smuzhiyun #define STIH407_GPU_SOFTRESET 22 50*4882a593Smuzhiyun #define STIH407_HVA_SOFTRESET 23 51*4882a593Smuzhiyun #define STIH407_ERAM_HVA_SOFTRESET 24 52*4882a593Smuzhiyun #define STIH407_LPM_SOFTRESET 25 53*4882a593Smuzhiyun #define STIH407_KEYSCAN_SOFTRESET 26 54*4882a593Smuzhiyun #define STIH407_USB2_PORT0_SOFTRESET 27 55*4882a593Smuzhiyun #define STIH407_USB2_PORT1_SOFTRESET 28 56*4882a593Smuzhiyun #define STIH407_ST231_AUD_SOFTRESET 29 57*4882a593Smuzhiyun #define STIH407_ST231_DMU_SOFTRESET 30 58*4882a593Smuzhiyun #define STIH407_ST231_GP0_SOFTRESET 31 59*4882a593Smuzhiyun #define STIH407_ST231_GP1_SOFTRESET 32 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Picophy reset defines */ 62*4882a593Smuzhiyun #define STIH407_PICOPHY0_RESET 0 63*4882a593Smuzhiyun #define STIH407_PICOPHY1_RESET 1 64*4882a593Smuzhiyun #define STIH407_PICOPHY2_RESET 2 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ 67