1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * This header provides index for the HSDK reset controller. 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK 5*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define HSDK_APB_RESET 0 8*4882a593Smuzhiyun #define HSDK_AXI_RESET 1 9*4882a593Smuzhiyun #define HSDK_ETH_RESET 2 10*4882a593Smuzhiyun #define HSDK_USB_RESET 3 11*4882a593Smuzhiyun #define HSDK_SDIO_RESET 4 12*4882a593Smuzhiyun #define HSDK_HDMI_RESET 5 13*4882a593Smuzhiyun #define HSDK_GFX_RESET 6 14*4882a593Smuzhiyun #define HSDK_DMAC_RESET 7 15*4882a593Smuzhiyun #define HSDK_EBI_RESET 8 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ 18