1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Realtek RTD1295 reset controllers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017 Andreas Färber 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef DT_BINDINGS_RESET_RTD1295_H 8*4882a593Smuzhiyun #define DT_BINDINGS_RESET_RTD1295_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* soft reset 1 */ 11*4882a593Smuzhiyun #define RTD1295_RSTN_MISC 0 12*4882a593Smuzhiyun #define RTD1295_RSTN_NAT 1 13*4882a593Smuzhiyun #define RTD1295_RSTN_USB3_PHY0_POW 2 14*4882a593Smuzhiyun #define RTD1295_RSTN_GSPI 3 15*4882a593Smuzhiyun #define RTD1295_RSTN_USB3_P0_MDIO 4 16*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_0 5 17*4882a593Smuzhiyun #define RTD1295_RSTN_USB 6 18*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_PHY_0 7 19*4882a593Smuzhiyun #define RTD1295_RSTN_USB_PHY0 8 20*4882a593Smuzhiyun #define RTD1295_RSTN_USB_PHY1 9 21*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_PHY_POW_0 10 22*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_FUNC_EXIST_0 11 23*4882a593Smuzhiyun #define RTD1295_RSTN_HDMI 12 24*4882a593Smuzhiyun #define RTD1295_RSTN_VE1 13 25*4882a593Smuzhiyun #define RTD1295_RSTN_VE2 14 26*4882a593Smuzhiyun #define RTD1295_RSTN_VE3 15 27*4882a593Smuzhiyun #define RTD1295_RSTN_ETN 16 28*4882a593Smuzhiyun #define RTD1295_RSTN_AIO 17 29*4882a593Smuzhiyun #define RTD1295_RSTN_GPU 18 30*4882a593Smuzhiyun #define RTD1295_RSTN_TVE 19 31*4882a593Smuzhiyun #define RTD1295_RSTN_VO 20 32*4882a593Smuzhiyun #define RTD1295_RSTN_LVDS 21 33*4882a593Smuzhiyun #define RTD1295_RSTN_SE 22 34*4882a593Smuzhiyun #define RTD1295_RSTN_DCU 23 35*4882a593Smuzhiyun #define RTD1295_RSTN_DC_PHY 24 36*4882a593Smuzhiyun #define RTD1295_RSTN_CP 25 37*4882a593Smuzhiyun #define RTD1295_RSTN_MD 26 38*4882a593Smuzhiyun #define RTD1295_RSTN_TP 27 39*4882a593Smuzhiyun #define RTD1295_RSTN_AE 28 40*4882a593Smuzhiyun #define RTD1295_RSTN_NF 29 41*4882a593Smuzhiyun #define RTD1295_RSTN_MIPI 30 42*4882a593Smuzhiyun #define RTD1295_RSTN_RSA 31 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* soft reset 2 */ 45*4882a593Smuzhiyun #define RTD1295_RSTN_ACPU 0 46*4882a593Smuzhiyun #define RTD1295_RSTN_JPEG 1 47*4882a593Smuzhiyun #define RTD1295_RSTN_USB_PHY3 2 48*4882a593Smuzhiyun #define RTD1295_RSTN_USB_PHY2 3 49*4882a593Smuzhiyun #define RTD1295_RSTN_USB3_PHY1_POW 4 50*4882a593Smuzhiyun #define RTD1295_RSTN_USB3_P1_MDIO 5 51*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0_STITCH 6 52*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0_PHY 7 53*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0 8 54*4882a593Smuzhiyun #define RTD1295_RSTN_PCR_CNT 9 55*4882a593Smuzhiyun #define RTD1295_RSTN_CR 10 56*4882a593Smuzhiyun #define RTD1295_RSTN_EMMC 11 57*4882a593Smuzhiyun #define RTD1295_RSTN_SDIO 12 58*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0_CORE 13 59*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0_POWER 14 60*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0_NONSTICH 15 61*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1_PHY 16 62*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1 17 63*4882a593Smuzhiyun #define RTD1295_RSTN_I2C_5 18 64*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1_STITCH 19 65*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1_CORE 20 66*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1_POWER 21 67*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1_NONSTICH 22 68*4882a593Smuzhiyun #define RTD1295_RSTN_I2C_4 23 69*4882a593Smuzhiyun #define RTD1295_RSTN_I2C_3 24 70*4882a593Smuzhiyun #define RTD1295_RSTN_I2C_2 25 71*4882a593Smuzhiyun #define RTD1295_RSTN_I2C_1 26 72*4882a593Smuzhiyun #define RTD1295_RSTN_UR2 27 73*4882a593Smuzhiyun #define RTD1295_RSTN_UR1 28 74*4882a593Smuzhiyun #define RTD1295_RSTN_MISC_SC 29 75*4882a593Smuzhiyun #define RTD1295_RSTN_CBUS_TX 30 76*4882a593Smuzhiyun #define RTD1295_RSTN_SDS_PHY 31 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* soft reset 3 */ 79*4882a593Smuzhiyun #define RTD1295_RSTN_SB2 0 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* soft reset 4 */ 82*4882a593Smuzhiyun #define RTD1295_RSTN_DCPHY_CRT 0 83*4882a593Smuzhiyun #define RTD1295_RSTN_DCPHY_ALERT_RX 1 84*4882a593Smuzhiyun #define RTD1295_RSTN_DCPHY_PTR 2 85*4882a593Smuzhiyun #define RTD1295_RSTN_DCPHY_LDO 3 86*4882a593Smuzhiyun #define RTD1295_RSTN_DCPHY_SSC_DIG 4 87*4882a593Smuzhiyun #define RTD1295_RSTN_HDMIRX 5 88*4882a593Smuzhiyun #define RTD1295_RSTN_CBUSRX 6 89*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_PHY_POW_1 7 90*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_FUNC_EXIST_1 8 91*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_PHY_1 9 92*4882a593Smuzhiyun #define RTD1295_RSTN_SATA_1 10 93*4882a593Smuzhiyun #define RTD1295_RSTN_FAN 11 94*4882a593Smuzhiyun #define RTD1295_RSTN_HDMIRX_WRAP 12 95*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE0_PHY_MDIO 13 96*4882a593Smuzhiyun #define RTD1295_RSTN_PCIE1_PHY_MDIO 14 97*4882a593Smuzhiyun #define RTD1295_RSTN_DISP 15 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* iso reset */ 100*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_IR 1 101*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_CEC0 2 102*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_CEC1 3 103*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_DP 4 104*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_CBUSTX 5 105*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_CBUSRX 6 106*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_EFUSE 7 107*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_UR0 8 108*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_GMAC 9 109*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_GPHY 10 110*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_I2C_0 11 111*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_I2C_1 12 112*4882a593Smuzhiyun #define RTD1295_ISO_RSTN_CBUS 13 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif 115