1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_MSM_MMCC_8960_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define VPE_AXI_RESET 0 10*4882a593Smuzhiyun #define IJPEG_AXI_RESET 1 11*4882a593Smuzhiyun #define MPD_AXI_RESET 2 12*4882a593Smuzhiyun #define VFE_AXI_RESET 3 13*4882a593Smuzhiyun #define SP_AXI_RESET 4 14*4882a593Smuzhiyun #define VCODEC_AXI_RESET 5 15*4882a593Smuzhiyun #define ROT_AXI_RESET 6 16*4882a593Smuzhiyun #define VCODEC_AXI_A_RESET 7 17*4882a593Smuzhiyun #define VCODEC_AXI_B_RESET 8 18*4882a593Smuzhiyun #define FAB_S3_AXI_RESET 9 19*4882a593Smuzhiyun #define FAB_S2_AXI_RESET 10 20*4882a593Smuzhiyun #define FAB_S1_AXI_RESET 11 21*4882a593Smuzhiyun #define FAB_S0_AXI_RESET 12 22*4882a593Smuzhiyun #define SMMU_GFX3D_ABH_RESET 13 23*4882a593Smuzhiyun #define SMMU_VPE_AHB_RESET 14 24*4882a593Smuzhiyun #define SMMU_VFE_AHB_RESET 15 25*4882a593Smuzhiyun #define SMMU_ROT_AHB_RESET 16 26*4882a593Smuzhiyun #define SMMU_VCODEC_B_AHB_RESET 17 27*4882a593Smuzhiyun #define SMMU_VCODEC_A_AHB_RESET 18 28*4882a593Smuzhiyun #define SMMU_MDP1_AHB_RESET 19 29*4882a593Smuzhiyun #define SMMU_MDP0_AHB_RESET 20 30*4882a593Smuzhiyun #define SMMU_JPEGD_AHB_RESET 21 31*4882a593Smuzhiyun #define SMMU_IJPEG_AHB_RESET 22 32*4882a593Smuzhiyun #define SMMU_GFX2D0_AHB_RESET 23 33*4882a593Smuzhiyun #define SMMU_GFX2D1_AHB_RESET 24 34*4882a593Smuzhiyun #define APU_AHB_RESET 25 35*4882a593Smuzhiyun #define CSI_AHB_RESET 26 36*4882a593Smuzhiyun #define TV_ENC_AHB_RESET 27 37*4882a593Smuzhiyun #define VPE_AHB_RESET 28 38*4882a593Smuzhiyun #define FABRIC_AHB_RESET 29 39*4882a593Smuzhiyun #define GFX2D0_AHB_RESET 30 40*4882a593Smuzhiyun #define GFX2D1_AHB_RESET 31 41*4882a593Smuzhiyun #define GFX3D_AHB_RESET 32 42*4882a593Smuzhiyun #define HDMI_AHB_RESET 33 43*4882a593Smuzhiyun #define MSSS_IMEM_AHB_RESET 34 44*4882a593Smuzhiyun #define IJPEG_AHB_RESET 35 45*4882a593Smuzhiyun #define DSI_M_AHB_RESET 36 46*4882a593Smuzhiyun #define DSI_S_AHB_RESET 37 47*4882a593Smuzhiyun #define JPEGD_AHB_RESET 38 48*4882a593Smuzhiyun #define MDP_AHB_RESET 39 49*4882a593Smuzhiyun #define ROT_AHB_RESET 40 50*4882a593Smuzhiyun #define VCODEC_AHB_RESET 41 51*4882a593Smuzhiyun #define VFE_AHB_RESET 42 52*4882a593Smuzhiyun #define DSI2_M_AHB_RESET 43 53*4882a593Smuzhiyun #define DSI2_S_AHB_RESET 44 54*4882a593Smuzhiyun #define CSIPHY2_RESET 45 55*4882a593Smuzhiyun #define CSI_PIX1_RESET 46 56*4882a593Smuzhiyun #define CSIPHY0_RESET 47 57*4882a593Smuzhiyun #define CSIPHY1_RESET 48 58*4882a593Smuzhiyun #define DSI2_RESET 49 59*4882a593Smuzhiyun #define VFE_CSI_RESET 50 60*4882a593Smuzhiyun #define MDP_RESET 51 61*4882a593Smuzhiyun #define AMP_RESET 52 62*4882a593Smuzhiyun #define JPEGD_RESET 53 63*4882a593Smuzhiyun #define CSI1_RESET 54 64*4882a593Smuzhiyun #define VPE_RESET 55 65*4882a593Smuzhiyun #define MMSS_FABRIC_RESET 56 66*4882a593Smuzhiyun #define VFE_RESET 57 67*4882a593Smuzhiyun #define GFX2D0_RESET 58 68*4882a593Smuzhiyun #define GFX2D1_RESET 59 69*4882a593Smuzhiyun #define GFX3D_RESET 60 70*4882a593Smuzhiyun #define HDMI_RESET 61 71*4882a593Smuzhiyun #define MMSS_IMEM_RESET 62 72*4882a593Smuzhiyun #define IJPEG_RESET 63 73*4882a593Smuzhiyun #define CSI0_RESET 64 74*4882a593Smuzhiyun #define DSI_RESET 65 75*4882a593Smuzhiyun #define VCODEC_RESET 66 76*4882a593Smuzhiyun #define MDP_TV_RESET 67 77*4882a593Smuzhiyun #define MDP_VSYNC_RESET 68 78*4882a593Smuzhiyun #define ROT_RESET 69 79*4882a593Smuzhiyun #define TV_HDMI_RESET 70 80*4882a593Smuzhiyun #define TV_ENC_RESET 71 81*4882a593Smuzhiyun #define CSI2_RESET 72 82*4882a593Smuzhiyun #define CSI_RDI1_RESET 73 83*4882a593Smuzhiyun #define CSI_RDI2_RESET 74 84*4882a593Smuzhiyun #define GFX3D_AXI_RESET 75 85*4882a593Smuzhiyun #define VCAP_AXI_RESET 76 86*4882a593Smuzhiyun #define SMMU_VCAP_AHB_RESET 77 87*4882a593Smuzhiyun #define VCAP_AHB_RESET 78 88*4882a593Smuzhiyun #define CSI_RDI_RESET 79 89*4882a593Smuzhiyun #define CSI_PIX_RESET 80 90*4882a593Smuzhiyun #define VCAP_NPL_RESET 81 91*4882a593Smuzhiyun #define VCAP_RESET 82 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif 94