1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_APQ_MMCC_8084_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MMSS_SPDM_RESET 0 10*4882a593Smuzhiyun #define MMSS_SPDM_RM_RESET 1 11*4882a593Smuzhiyun #define VENUS0_RESET 2 12*4882a593Smuzhiyun #define VPU_RESET 3 13*4882a593Smuzhiyun #define MDSS_RESET 4 14*4882a593Smuzhiyun #define AVSYNC_RESET 5 15*4882a593Smuzhiyun #define CAMSS_PHY0_RESET 6 16*4882a593Smuzhiyun #define CAMSS_PHY1_RESET 7 17*4882a593Smuzhiyun #define CAMSS_PHY2_RESET 8 18*4882a593Smuzhiyun #define CAMSS_CSI0_RESET 9 19*4882a593Smuzhiyun #define CAMSS_CSI0PHY_RESET 10 20*4882a593Smuzhiyun #define CAMSS_CSI0RDI_RESET 11 21*4882a593Smuzhiyun #define CAMSS_CSI0PIX_RESET 12 22*4882a593Smuzhiyun #define CAMSS_CSI1_RESET 13 23*4882a593Smuzhiyun #define CAMSS_CSI1PHY_RESET 14 24*4882a593Smuzhiyun #define CAMSS_CSI1RDI_RESET 15 25*4882a593Smuzhiyun #define CAMSS_CSI1PIX_RESET 16 26*4882a593Smuzhiyun #define CAMSS_CSI2_RESET 17 27*4882a593Smuzhiyun #define CAMSS_CSI2PHY_RESET 18 28*4882a593Smuzhiyun #define CAMSS_CSI2RDI_RESET 19 29*4882a593Smuzhiyun #define CAMSS_CSI2PIX_RESET 20 30*4882a593Smuzhiyun #define CAMSS_CSI3_RESET 21 31*4882a593Smuzhiyun #define CAMSS_CSI3PHY_RESET 22 32*4882a593Smuzhiyun #define CAMSS_CSI3RDI_RESET 23 33*4882a593Smuzhiyun #define CAMSS_CSI3PIX_RESET 24 34*4882a593Smuzhiyun #define CAMSS_ISPIF_RESET 25 35*4882a593Smuzhiyun #define CAMSS_CCI_RESET 26 36*4882a593Smuzhiyun #define CAMSS_MCLK0_RESET 27 37*4882a593Smuzhiyun #define CAMSS_MCLK1_RESET 28 38*4882a593Smuzhiyun #define CAMSS_MCLK2_RESET 29 39*4882a593Smuzhiyun #define CAMSS_MCLK3_RESET 30 40*4882a593Smuzhiyun #define CAMSS_GP0_RESET 31 41*4882a593Smuzhiyun #define CAMSS_GP1_RESET 32 42*4882a593Smuzhiyun #define CAMSS_TOP_RESET 33 43*4882a593Smuzhiyun #define CAMSS_AHB_RESET 34 44*4882a593Smuzhiyun #define CAMSS_MICRO_RESET 35 45*4882a593Smuzhiyun #define CAMSS_JPEG_RESET 36 46*4882a593Smuzhiyun #define CAMSS_VFE_RESET 37 47*4882a593Smuzhiyun #define CAMSS_CSI_VFE0_RESET 38 48*4882a593Smuzhiyun #define CAMSS_CSI_VFE1_RESET 39 49*4882a593Smuzhiyun #define OXILI_RESET 40 50*4882a593Smuzhiyun #define OXILICX_RESET 41 51*4882a593Smuzhiyun #define OCMEMCX_RESET 42 52*4882a593Smuzhiyun #define MMSS_RBCRP_RESET 43 53*4882a593Smuzhiyun #define MMSSNOCAHB_RESET 44 54*4882a593Smuzhiyun #define MMSSNOCAXI_RESET 45 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57