1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2020 Linaro Limited 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_MSM_GCC_8939_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GCC_BLSP1_BCR 0 10*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_BCR 1 11*4882a593Smuzhiyun #define GCC_BLSP1_UART1_BCR 2 12*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_BCR 3 13*4882a593Smuzhiyun #define GCC_BLSP1_UART2_BCR 4 14*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_BCR 5 15*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_BCR 6 16*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_BCR 7 17*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_BCR 8 18*4882a593Smuzhiyun #define GCC_IMEM_BCR 9 19*4882a593Smuzhiyun #define GCC_SMMU_BCR 10 20*4882a593Smuzhiyun #define GCC_APSS_TCU_BCR 11 21*4882a593Smuzhiyun #define GCC_SMMU_XPU_BCR 12 22*4882a593Smuzhiyun #define GCC_PCNOC_TBU_BCR 13 23*4882a593Smuzhiyun #define GCC_PRNG_BCR 14 24*4882a593Smuzhiyun #define GCC_BOOT_ROM_BCR 15 25*4882a593Smuzhiyun #define GCC_CRYPTO_BCR 16 26*4882a593Smuzhiyun #define GCC_SEC_CTRL_BCR 17 27*4882a593Smuzhiyun #define GCC_AUDIO_CORE_BCR 18 28*4882a593Smuzhiyun #define GCC_ULT_AUDIO_BCR 19 29*4882a593Smuzhiyun #define GCC_DEHR_BCR 20 30*4882a593Smuzhiyun #define GCC_SYSTEM_NOC_BCR 21 31*4882a593Smuzhiyun #define GCC_PCNOC_BCR 22 32*4882a593Smuzhiyun #define GCC_TCSR_BCR 23 33*4882a593Smuzhiyun #define GCC_QDSS_BCR 24 34*4882a593Smuzhiyun #define GCC_DCD_BCR 25 35*4882a593Smuzhiyun #define GCC_MSG_RAM_BCR 26 36*4882a593Smuzhiyun #define GCC_MPM_BCR 27 37*4882a593Smuzhiyun #define GCC_SPMI_BCR 28 38*4882a593Smuzhiyun #define GCC_SPDM_BCR 29 39*4882a593Smuzhiyun #define GCC_MM_SPDM_BCR 30 40*4882a593Smuzhiyun #define GCC_BIMC_BCR 31 41*4882a593Smuzhiyun #define GCC_RBCPR_BCR 32 42*4882a593Smuzhiyun #define GCC_TLMM_BCR 33 43*4882a593Smuzhiyun #define GCC_USB_HS_BCR 34 44*4882a593Smuzhiyun #define GCC_USB2A_PHY_BCR 35 45*4882a593Smuzhiyun #define GCC_SDCC1_BCR 36 46*4882a593Smuzhiyun #define GCC_SDCC2_BCR 37 47*4882a593Smuzhiyun #define GCC_PDM_BCR 38 48*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_BCR 39 49*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 50*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 51*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 52*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 53*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 54*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 55*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 56*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 57*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 58*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 59*4882a593Smuzhiyun #define GCC_MMSS_BCR 50 60*4882a593Smuzhiyun #define GCC_VENUS0_BCR 51 61*4882a593Smuzhiyun #define GCC_MDSS_BCR 52 62*4882a593Smuzhiyun #define GCC_CAMSS_PHY0_BCR 53 63*4882a593Smuzhiyun #define GCC_CAMSS_CSI0_BCR 54 64*4882a593Smuzhiyun #define GCC_CAMSS_CSI0PHY_BCR 55 65*4882a593Smuzhiyun #define GCC_CAMSS_CSI0RDI_BCR 56 66*4882a593Smuzhiyun #define GCC_CAMSS_CSI0PIX_BCR 57 67*4882a593Smuzhiyun #define GCC_CAMSS_PHY1_BCR 58 68*4882a593Smuzhiyun #define GCC_CAMSS_CSI1_BCR 59 69*4882a593Smuzhiyun #define GCC_CAMSS_CSI1PHY_BCR 60 70*4882a593Smuzhiyun #define GCC_CAMSS_CSI1RDI_BCR 61 71*4882a593Smuzhiyun #define GCC_CAMSS_CSI1PIX_BCR 62 72*4882a593Smuzhiyun #define GCC_CAMSS_ISPIF_BCR 63 73*4882a593Smuzhiyun #define GCC_CAMSS_CCI_BCR 64 74*4882a593Smuzhiyun #define GCC_CAMSS_MCLK0_BCR 65 75*4882a593Smuzhiyun #define GCC_CAMSS_MCLK1_BCR 66 76*4882a593Smuzhiyun #define GCC_CAMSS_GP0_BCR 67 77*4882a593Smuzhiyun #define GCC_CAMSS_GP1_BCR 68 78*4882a593Smuzhiyun #define GCC_CAMSS_TOP_BCR 69 79*4882a593Smuzhiyun #define GCC_CAMSS_MICRO_BCR 70 80*4882a593Smuzhiyun #define GCC_CAMSS_JPEG_BCR 71 81*4882a593Smuzhiyun #define GCC_CAMSS_VFE_BCR 72 82*4882a593Smuzhiyun #define GCC_CAMSS_CSI_VFE0_BCR 73 83*4882a593Smuzhiyun #define GCC_OXILI_BCR 74 84*4882a593Smuzhiyun #define GCC_GMEM_BCR 75 85*4882a593Smuzhiyun #define GCC_CAMSS_AHB_BCR 76 86*4882a593Smuzhiyun #define GCC_MDP_TBU_BCR 77 87*4882a593Smuzhiyun #define GCC_GFX_TBU_BCR 78 88*4882a593Smuzhiyun #define GCC_GFX_TCU_BCR 79 89*4882a593Smuzhiyun #define GCC_MSS_TBU_AXI_BCR 80 90*4882a593Smuzhiyun #define GCC_MSS_TBU_GSS_AXI_BCR 81 91*4882a593Smuzhiyun #define GCC_MSS_TBU_Q6_AXI_BCR 82 92*4882a593Smuzhiyun #define GCC_GTCU_AHB_BCR 83 93*4882a593Smuzhiyun #define GCC_SMMU_CFG_BCR 84 94*4882a593Smuzhiyun #define GCC_VFE_TBU_BCR 85 95*4882a593Smuzhiyun #define GCC_VENUS_TBU_BCR 86 96*4882a593Smuzhiyun #define GCC_JPEG_TBU_BCR 87 97*4882a593Smuzhiyun #define GCC_PRONTO_TBU_BCR 88 98*4882a593Smuzhiyun #define GCC_SMMU_CATS_BCR 89 99*4882a593Smuzhiyun #define GCC_BLSP1_UART3_BCR 90 100*4882a593Smuzhiyun #define GCC_CAMSS_CSI2_BCR 91 101*4882a593Smuzhiyun #define GCC_CAMSS_CSI2PHY_BCR 92 102*4882a593Smuzhiyun #define GCC_CAMSS_CSI2RDI_BCR 93 103*4882a593Smuzhiyun #define GCC_CAMSS_CSI2PIX_BCR 94 104*4882a593Smuzhiyun #define GCC_USB_FS_BCR 95 105*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96 106*4882a593Smuzhiyun #define GCC_CAMSS_MCLK2_BCR 97 107*4882a593Smuzhiyun #define GCC_CPP_TBU_BCR 98 108*4882a593Smuzhiyun #define GCC_MDP_RT_TBU_BCR 99 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #endif 111