1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) BayLibre, SAS. 5*4882a593Smuzhiyun * Author : Neil Armstrong <narmstrong@baylibre.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_GCC_MDM9615_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SFAB_MSS_Q6_SW_RESET 0 12*4882a593Smuzhiyun #define SFAB_MSS_Q6_FW_RESET 1 13*4882a593Smuzhiyun #define QDSS_STM_RESET 2 14*4882a593Smuzhiyun #define AFAB_SMPSS_S_RESET 3 15*4882a593Smuzhiyun #define AFAB_SMPSS_M1_RESET 4 16*4882a593Smuzhiyun #define AFAB_SMPSS_M0_RESET 5 17*4882a593Smuzhiyun #define AFAB_EBI1_CH0_RESET 6 18*4882a593Smuzhiyun #define AFAB_EBI1_CH1_RESET 7 19*4882a593Smuzhiyun #define SFAB_ADM0_M0_RESET 8 20*4882a593Smuzhiyun #define SFAB_ADM0_M1_RESET 9 21*4882a593Smuzhiyun #define SFAB_ADM0_M2_RESET 10 22*4882a593Smuzhiyun #define ADM0_C2_RESET 11 23*4882a593Smuzhiyun #define ADM0_C1_RESET 12 24*4882a593Smuzhiyun #define ADM0_C0_RESET 13 25*4882a593Smuzhiyun #define ADM0_PBUS_RESET 14 26*4882a593Smuzhiyun #define ADM0_RESET 15 27*4882a593Smuzhiyun #define QDSS_CLKS_SW_RESET 16 28*4882a593Smuzhiyun #define QDSS_POR_RESET 17 29*4882a593Smuzhiyun #define QDSS_TSCTR_RESET 18 30*4882a593Smuzhiyun #define QDSS_HRESET_RESET 19 31*4882a593Smuzhiyun #define QDSS_AXI_RESET 20 32*4882a593Smuzhiyun #define QDSS_DBG_RESET 21 33*4882a593Smuzhiyun #define PCIE_A_RESET 22 34*4882a593Smuzhiyun #define PCIE_AUX_RESET 23 35*4882a593Smuzhiyun #define PCIE_H_RESET 24 36*4882a593Smuzhiyun #define SFAB_PCIE_M_RESET 25 37*4882a593Smuzhiyun #define SFAB_PCIE_S_RESET 26 38*4882a593Smuzhiyun #define SFAB_MSS_M_RESET 27 39*4882a593Smuzhiyun #define SFAB_USB3_M_RESET 28 40*4882a593Smuzhiyun #define SFAB_RIVA_M_RESET 29 41*4882a593Smuzhiyun #define SFAB_LPASS_RESET 30 42*4882a593Smuzhiyun #define SFAB_AFAB_M_RESET 31 43*4882a593Smuzhiyun #define AFAB_SFAB_M0_RESET 32 44*4882a593Smuzhiyun #define AFAB_SFAB_M1_RESET 33 45*4882a593Smuzhiyun #define SFAB_SATA_S_RESET 34 46*4882a593Smuzhiyun #define SFAB_DFAB_M_RESET 35 47*4882a593Smuzhiyun #define DFAB_SFAB_M_RESET 36 48*4882a593Smuzhiyun #define DFAB_SWAY0_RESET 37 49*4882a593Smuzhiyun #define DFAB_SWAY1_RESET 38 50*4882a593Smuzhiyun #define DFAB_ARB0_RESET 39 51*4882a593Smuzhiyun #define DFAB_ARB1_RESET 40 52*4882a593Smuzhiyun #define PPSS_PROC_RESET 41 53*4882a593Smuzhiyun #define PPSS_RESET 42 54*4882a593Smuzhiyun #define DMA_BAM_RESET 43 55*4882a593Smuzhiyun #define SPS_TIC_H_RESET 44 56*4882a593Smuzhiyun #define SLIMBUS_H_RESET 45 57*4882a593Smuzhiyun #define SFAB_CFPB_M_RESET 46 58*4882a593Smuzhiyun #define SFAB_CFPB_S_RESET 47 59*4882a593Smuzhiyun #define TSIF_H_RESET 48 60*4882a593Smuzhiyun #define CE1_H_RESET 49 61*4882a593Smuzhiyun #define CE1_CORE_RESET 50 62*4882a593Smuzhiyun #define CE1_SLEEP_RESET 51 63*4882a593Smuzhiyun #define CE2_H_RESET 52 64*4882a593Smuzhiyun #define CE2_CORE_RESET 53 65*4882a593Smuzhiyun #define SFAB_SFPB_M_RESET 54 66*4882a593Smuzhiyun #define SFAB_SFPB_S_RESET 55 67*4882a593Smuzhiyun #define RPM_PROC_RESET 56 68*4882a593Smuzhiyun #define PMIC_SSBI2_RESET 57 69*4882a593Smuzhiyun #define SDC1_RESET 58 70*4882a593Smuzhiyun #define SDC2_RESET 59 71*4882a593Smuzhiyun #define SDC3_RESET 60 72*4882a593Smuzhiyun #define SDC4_RESET 61 73*4882a593Smuzhiyun #define SDC5_RESET 62 74*4882a593Smuzhiyun #define DFAB_A2_RESET 63 75*4882a593Smuzhiyun #define USB_HS1_RESET 64 76*4882a593Smuzhiyun #define USB_HSIC_RESET 65 77*4882a593Smuzhiyun #define USB_FS1_XCVR_RESET 66 78*4882a593Smuzhiyun #define USB_FS1_RESET 67 79*4882a593Smuzhiyun #define USB_FS2_XCVR_RESET 68 80*4882a593Smuzhiyun #define USB_FS2_RESET 69 81*4882a593Smuzhiyun #define GSBI1_RESET 70 82*4882a593Smuzhiyun #define GSBI2_RESET 71 83*4882a593Smuzhiyun #define GSBI3_RESET 72 84*4882a593Smuzhiyun #define GSBI4_RESET 73 85*4882a593Smuzhiyun #define GSBI5_RESET 74 86*4882a593Smuzhiyun #define GSBI6_RESET 75 87*4882a593Smuzhiyun #define GSBI7_RESET 76 88*4882a593Smuzhiyun #define GSBI8_RESET 77 89*4882a593Smuzhiyun #define GSBI9_RESET 78 90*4882a593Smuzhiyun #define GSBI10_RESET 79 91*4882a593Smuzhiyun #define GSBI11_RESET 80 92*4882a593Smuzhiyun #define GSBI12_RESET 81 93*4882a593Smuzhiyun #define SPDM_RESET 82 94*4882a593Smuzhiyun #define TLMM_H_RESET 83 95*4882a593Smuzhiyun #define SFAB_MSS_S_RESET 84 96*4882a593Smuzhiyun #define MSS_SLP_RESET 85 97*4882a593Smuzhiyun #define MSS_Q6SW_JTAG_RESET 86 98*4882a593Smuzhiyun #define MSS_Q6FW_JTAG_RESET 87 99*4882a593Smuzhiyun #define MSS_RESET 88 100*4882a593Smuzhiyun #define SATA_H_RESET 89 101*4882a593Smuzhiyun #define SATA_RXOOB_RESE 90 102*4882a593Smuzhiyun #define SATA_PMALIVE_RESET 91 103*4882a593Smuzhiyun #define SATA_SFAB_M_RESET 92 104*4882a593Smuzhiyun #define TSSC_RESET 93 105*4882a593Smuzhiyun #define PDM_RESET 94 106*4882a593Smuzhiyun #define MPM_H_RESET 95 107*4882a593Smuzhiyun #define MPM_RESET 96 108*4882a593Smuzhiyun #define SFAB_SMPSS_S_RESET 97 109*4882a593Smuzhiyun #define PRNG_RESET 98 110*4882a593Smuzhiyun #define RIVA_RESET 99 111*4882a593Smuzhiyun #define USB_HS3_RESET 100 112*4882a593Smuzhiyun #define USB_HS4_RESET 101 113*4882a593Smuzhiyun #define CE3_RESET 102 114*4882a593Smuzhiyun #define PCIE_EXT_PCI_RESET 103 115*4882a593Smuzhiyun #define PCIE_PHY_RESET 104 116*4882a593Smuzhiyun #define PCIE_PCI_RESET 105 117*4882a593Smuzhiyun #define PCIE_POR_RESET 106 118*4882a593Smuzhiyun #define PCIE_HCLK_RESET 107 119*4882a593Smuzhiyun #define PCIE_ACLK_RESET 108 120*4882a593Smuzhiyun #define CE3_H_RESET 109 121*4882a593Smuzhiyun #define SFAB_CE3_M_RESET 110 122*4882a593Smuzhiyun #define SFAB_CE3_S_RESET 111 123*4882a593Smuzhiyun #define SATA_RESET 112 124*4882a593Smuzhiyun #define CE3_SLEEP_RESET 113 125*4882a593Smuzhiyun #define GSS_SLP_RESET 114 126*4882a593Smuzhiyun #define GSS_RESET 115 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #endif 129