1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_IPQ_GCC_6018_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GCC_BLSP1_BCR 0 10*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_BCR 1 11*4882a593Smuzhiyun #define GCC_BLSP1_UART1_BCR 2 12*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_BCR 3 13*4882a593Smuzhiyun #define GCC_BLSP1_UART2_BCR 4 14*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_BCR 5 15*4882a593Smuzhiyun #define GCC_BLSP1_UART3_BCR 6 16*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_BCR 7 17*4882a593Smuzhiyun #define GCC_BLSP1_UART4_BCR 8 18*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_BCR 9 19*4882a593Smuzhiyun #define GCC_BLSP1_UART5_BCR 10 20*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_BCR 11 21*4882a593Smuzhiyun #define GCC_BLSP1_UART6_BCR 12 22*4882a593Smuzhiyun #define GCC_IMEM_BCR 13 23*4882a593Smuzhiyun #define GCC_SMMU_BCR 14 24*4882a593Smuzhiyun #define GCC_APSS_TCU_BCR 15 25*4882a593Smuzhiyun #define GCC_SMMU_XPU_BCR 16 26*4882a593Smuzhiyun #define GCC_PCNOC_TBU_BCR 17 27*4882a593Smuzhiyun #define GCC_SMMU_CFG_BCR 18 28*4882a593Smuzhiyun #define GCC_PRNG_BCR 19 29*4882a593Smuzhiyun #define GCC_BOOT_ROM_BCR 20 30*4882a593Smuzhiyun #define GCC_CRYPTO_BCR 21 31*4882a593Smuzhiyun #define GCC_WCSS_BCR 22 32*4882a593Smuzhiyun #define GCC_WCSS_Q6_BCR 23 33*4882a593Smuzhiyun #define GCC_NSS_BCR 24 34*4882a593Smuzhiyun #define GCC_SEC_CTRL_BCR 25 35*4882a593Smuzhiyun #define GCC_DDRSS_BCR 26 36*4882a593Smuzhiyun #define GCC_SYSTEM_NOC_BCR 27 37*4882a593Smuzhiyun #define GCC_PCNOC_BCR 28 38*4882a593Smuzhiyun #define GCC_TCSR_BCR 29 39*4882a593Smuzhiyun #define GCC_QDSS_BCR 30 40*4882a593Smuzhiyun #define GCC_DCD_BCR 31 41*4882a593Smuzhiyun #define GCC_MSG_RAM_BCR 32 42*4882a593Smuzhiyun #define GCC_MPM_BCR 33 43*4882a593Smuzhiyun #define GCC_SPDM_BCR 34 44*4882a593Smuzhiyun #define GCC_RBCPR_BCR 35 45*4882a593Smuzhiyun #define GCC_RBCPR_MX_BCR 36 46*4882a593Smuzhiyun #define GCC_TLMM_BCR 37 47*4882a593Smuzhiyun #define GCC_RBCPR_WCSS_BCR 38 48*4882a593Smuzhiyun #define GCC_USB0_PHY_BCR 39 49*4882a593Smuzhiyun #define GCC_USB3PHY_0_PHY_BCR 40 50*4882a593Smuzhiyun #define GCC_USB0_BCR 41 51*4882a593Smuzhiyun #define GCC_USB1_BCR 42 52*4882a593Smuzhiyun #define GCC_QUSB2_0_PHY_BCR 43 53*4882a593Smuzhiyun #define GCC_QUSB2_1_PHY_BCR 44 54*4882a593Smuzhiyun #define GCC_SDCC1_BCR 45 55*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_BCR 46 56*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT1_BCR 47 57*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT2_BCR 48 58*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT0_BCR 49 59*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT1_BCR 50 60*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT2_BCR 51 61*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT3_BCR 52 62*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT4_BCR 53 63*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT5_BCR 54 64*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT6_BCR 55 65*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT7_BCR 56 66*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT8_BCR 57 67*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT9_BCR 58 68*4882a593Smuzhiyun #define GCC_UNIPHY0_BCR 59 69*4882a593Smuzhiyun #define GCC_UNIPHY1_BCR 60 70*4882a593Smuzhiyun #define GCC_CMN_12GPLL_BCR 61 71*4882a593Smuzhiyun #define GCC_QPIC_BCR 62 72*4882a593Smuzhiyun #define GCC_MDIO_BCR 63 73*4882a593Smuzhiyun #define GCC_WCSS_CORE_TBU_BCR 64 74*4882a593Smuzhiyun #define GCC_WCSS_Q6_TBU_BCR 65 75*4882a593Smuzhiyun #define GCC_USB0_TBU_BCR 66 76*4882a593Smuzhiyun #define GCC_PCIE0_TBU_BCR 67 77*4882a593Smuzhiyun #define GCC_PCIE0_BCR 68 78*4882a593Smuzhiyun #define GCC_PCIE0_PHY_BCR 69 79*4882a593Smuzhiyun #define GCC_PCIE0PHY_PHY_BCR 70 80*4882a593Smuzhiyun #define GCC_PCIE0_LINK_DOWN_BCR 71 81*4882a593Smuzhiyun #define GCC_DCC_BCR 72 82*4882a593Smuzhiyun #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73 83*4882a593Smuzhiyun #define GCC_SMMU_CATS_BCR 74 84*4882a593Smuzhiyun #define GCC_UBI0_AXI_ARES 75 85*4882a593Smuzhiyun #define GCC_UBI0_AHB_ARES 76 86*4882a593Smuzhiyun #define GCC_UBI0_NC_AXI_ARES 77 87*4882a593Smuzhiyun #define GCC_UBI0_DBG_ARES 78 88*4882a593Smuzhiyun #define GCC_UBI0_CORE_CLAMP_ENABLE 79 89*4882a593Smuzhiyun #define GCC_UBI0_CLKRST_CLAMP_ENABLE 80 90*4882a593Smuzhiyun #define GCC_UBI0_UTCM_ARES 81 91*4882a593Smuzhiyun #define GCC_NSS_CFG_ARES 82 92*4882a593Smuzhiyun #define GCC_NSS_NOC_ARES 83 93*4882a593Smuzhiyun #define GCC_NSS_CRYPTO_ARES 84 94*4882a593Smuzhiyun #define GCC_NSS_CSR_ARES 85 95*4882a593Smuzhiyun #define GCC_NSS_CE_APB_ARES 86 96*4882a593Smuzhiyun #define GCC_NSS_CE_AXI_ARES 87 97*4882a593Smuzhiyun #define GCC_NSSNOC_CE_APB_ARES 88 98*4882a593Smuzhiyun #define GCC_NSSNOC_CE_AXI_ARES 89 99*4882a593Smuzhiyun #define GCC_NSSNOC_UBI0_AHB_ARES 90 100*4882a593Smuzhiyun #define GCC_NSSNOC_SNOC_ARES 91 101*4882a593Smuzhiyun #define GCC_NSSNOC_CRYPTO_ARES 92 102*4882a593Smuzhiyun #define GCC_NSSNOC_ATB_ARES 93 103*4882a593Smuzhiyun #define GCC_NSSNOC_QOSGEN_REF_ARES 94 104*4882a593Smuzhiyun #define GCC_NSSNOC_TIMEOUT_REF_ARES 95 105*4882a593Smuzhiyun #define GCC_PCIE0_PIPE_ARES 96 106*4882a593Smuzhiyun #define GCC_PCIE0_SLEEP_ARES 97 107*4882a593Smuzhiyun #define GCC_PCIE0_CORE_STICKY_ARES 98 108*4882a593Smuzhiyun #define GCC_PCIE0_AXI_MASTER_ARES 99 109*4882a593Smuzhiyun #define GCC_PCIE0_AXI_SLAVE_ARES 100 110*4882a593Smuzhiyun #define GCC_PCIE0_AHB_ARES 101 111*4882a593Smuzhiyun #define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102 112*4882a593Smuzhiyun #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103 113*4882a593Smuzhiyun #define GCC_PPE_FULL_RESET 104 114*4882a593Smuzhiyun #define GCC_UNIPHY0_SOFT_RESET 105 115*4882a593Smuzhiyun #define GCC_UNIPHY0_XPCS_RESET 106 116*4882a593Smuzhiyun #define GCC_UNIPHY1_SOFT_RESET 107 117*4882a593Smuzhiyun #define GCC_UNIPHY1_XPCS_RESET 108 118*4882a593Smuzhiyun #define GCC_EDMA_HW_RESET 109 119*4882a593Smuzhiyun #define GCC_ADSS_BCR 110 120*4882a593Smuzhiyun #define GCC_NSS_NOC_TBU_BCR 111 121*4882a593Smuzhiyun #define GCC_NSSPORT1_RESET 112 122*4882a593Smuzhiyun #define GCC_NSSPORT2_RESET 113 123*4882a593Smuzhiyun #define GCC_NSSPORT3_RESET 114 124*4882a593Smuzhiyun #define GCC_NSSPORT4_RESET 115 125*4882a593Smuzhiyun #define GCC_NSSPORT5_RESET 116 126*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT1_ARES 117 127*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT2_ARES 118 128*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT3_ARES 119 129*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT4_ARES 120 130*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT5_ARES 121 131*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT_4_5_RESET 122 132*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT_4_RESET 123 133*4882a593Smuzhiyun #define GCC_LPASS_BCR 124 134*4882a593Smuzhiyun #define GCC_UBI32_TBU_BCR 125 135*4882a593Smuzhiyun #define GCC_LPASS_TBU_BCR 126 136*4882a593Smuzhiyun #define GCC_WCSSAON_RESET 127 137*4882a593Smuzhiyun #define GCC_LPASS_Q6_AXIM_ARES 128 138*4882a593Smuzhiyun #define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129 139*4882a593Smuzhiyun #define GCC_LPASS_Q6SS_TRIG_ARES 130 140*4882a593Smuzhiyun #define GCC_LPASS_Q6_ATBM_AT_ARES 131 141*4882a593Smuzhiyun #define GCC_LPASS_Q6_PCLKDBG_ARES 132 142*4882a593Smuzhiyun #define GCC_LPASS_CORE_AXIM_ARES 133 143*4882a593Smuzhiyun #define GCC_LPASS_SNOC_CFG_ARES 134 144*4882a593Smuzhiyun #define GCC_WCSS_DBG_ARES 135 145*4882a593Smuzhiyun #define GCC_WCSS_ECAHB_ARES 136 146*4882a593Smuzhiyun #define GCC_WCSS_ACMT_ARES 137 147*4882a593Smuzhiyun #define GCC_WCSS_DBG_BDG_ARES 138 148*4882a593Smuzhiyun #define GCC_WCSS_AHB_S_ARES 139 149*4882a593Smuzhiyun #define GCC_WCSS_AXI_M_ARES 140 150*4882a593Smuzhiyun #define GCC_Q6SS_DBG_ARES 141 151*4882a593Smuzhiyun #define GCC_Q6_AHB_S_ARES 142 152*4882a593Smuzhiyun #define GCC_Q6_AHB_ARES 143 153*4882a593Smuzhiyun #define GCC_Q6_AXIM2_ARES 144 154*4882a593Smuzhiyun #define GCC_Q6_AXIM_ARES 145 155*4882a593Smuzhiyun #define GCC_UBI0_CORE_ARES 146 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #endif 158