1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_MSM_GCC_8974_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GCC_SYSTEM_NOC_BCR 0 10*4882a593Smuzhiyun #define GCC_CONFIG_NOC_BCR 1 11*4882a593Smuzhiyun #define GCC_PERIPH_NOC_BCR 2 12*4882a593Smuzhiyun #define GCC_IMEM_BCR 3 13*4882a593Smuzhiyun #define GCC_MMSS_BCR 4 14*4882a593Smuzhiyun #define GCC_QDSS_BCR 5 15*4882a593Smuzhiyun #define GCC_USB_30_BCR 6 16*4882a593Smuzhiyun #define GCC_USB3_PHY_BCR 7 17*4882a593Smuzhiyun #define GCC_USB_HS_HSIC_BCR 8 18*4882a593Smuzhiyun #define GCC_USB_HS_BCR 9 19*4882a593Smuzhiyun #define GCC_USB2A_PHY_BCR 10 20*4882a593Smuzhiyun #define GCC_USB2B_PHY_BCR 11 21*4882a593Smuzhiyun #define GCC_SDCC1_BCR 12 22*4882a593Smuzhiyun #define GCC_SDCC2_BCR 13 23*4882a593Smuzhiyun #define GCC_SDCC3_BCR 14 24*4882a593Smuzhiyun #define GCC_SDCC4_BCR 15 25*4882a593Smuzhiyun #define GCC_BLSP1_BCR 16 26*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_BCR 17 27*4882a593Smuzhiyun #define GCC_BLSP1_UART1_BCR 18 28*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_BCR 19 29*4882a593Smuzhiyun #define GCC_BLSP1_UART2_BCR 20 30*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_BCR 21 31*4882a593Smuzhiyun #define GCC_BLSP1_UART3_BCR 22 32*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_BCR 23 33*4882a593Smuzhiyun #define GCC_BLSP1_UART4_BCR 24 34*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_BCR 25 35*4882a593Smuzhiyun #define GCC_BLSP1_UART5_BCR 26 36*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_BCR 27 37*4882a593Smuzhiyun #define GCC_BLSP1_UART6_BCR 28 38*4882a593Smuzhiyun #define GCC_BLSP2_BCR 29 39*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_BCR 30 40*4882a593Smuzhiyun #define GCC_BLSP2_UART1_BCR 31 41*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_BCR 32 42*4882a593Smuzhiyun #define GCC_BLSP2_UART2_BCR 33 43*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_BCR 34 44*4882a593Smuzhiyun #define GCC_BLSP2_UART3_BCR 35 45*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_BCR 36 46*4882a593Smuzhiyun #define GCC_BLSP2_UART4_BCR 37 47*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_BCR 38 48*4882a593Smuzhiyun #define GCC_BLSP2_UART5_BCR 39 49*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_BCR 40 50*4882a593Smuzhiyun #define GCC_BLSP2_UART6_BCR 41 51*4882a593Smuzhiyun #define GCC_PDM_BCR 42 52*4882a593Smuzhiyun #define GCC_BAM_DMA_BCR 43 53*4882a593Smuzhiyun #define GCC_TSIF_BCR 44 54*4882a593Smuzhiyun #define GCC_TCSR_BCR 45 55*4882a593Smuzhiyun #define GCC_BOOT_ROM_BCR 46 56*4882a593Smuzhiyun #define GCC_MSG_RAM_BCR 47 57*4882a593Smuzhiyun #define GCC_TLMM_BCR 48 58*4882a593Smuzhiyun #define GCC_MPM_BCR 49 59*4882a593Smuzhiyun #define GCC_SEC_CTRL_BCR 50 60*4882a593Smuzhiyun #define GCC_SPMI_BCR 51 61*4882a593Smuzhiyun #define GCC_SPDM_BCR 52 62*4882a593Smuzhiyun #define GCC_CE1_BCR 53 63*4882a593Smuzhiyun #define GCC_CE2_BCR 54 64*4882a593Smuzhiyun #define GCC_BIMC_BCR 55 65*4882a593Smuzhiyun #define GCC_MPM_NON_AHB_RESET 56 66*4882a593Smuzhiyun #define GCC_MPM_AHB_RESET 57 67*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_BCR 58 68*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT2_BCR 59 69*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT0_BCR 60 70*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT1_BCR 61 71*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT2_BCR 62 72*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT3_BCR 63 73*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT4_BCR 64 74*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT0_BCR 65 75*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT1_BCR 66 76*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT2_BCR 67 77*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT3_BCR 68 78*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT4_BCR 69 79*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT5_BCR 70 80*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT6_BCR 71 81*4882a593Smuzhiyun #define GCC_DEHR_BCR 72 82*4882a593Smuzhiyun #define GCC_RBCPR_BCR 73 83*4882a593Smuzhiyun #define GCC_MSS_RESTART 74 84*4882a593Smuzhiyun #define GCC_LPASS_RESTART 75 85*4882a593Smuzhiyun #define GCC_WCSS_RESTART 76 86*4882a593Smuzhiyun #define GCC_VENUS_RESTART 77 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif 89