1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for the reset controller 4*4882a593Smuzhiyun * present in the Pistachio SoC 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _PISTACHIO_RESETS_H 8*4882a593Smuzhiyun #define _PISTACHIO_RESETS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define PISTACHIO_RESET_I2C0 0 11*4882a593Smuzhiyun #define PISTACHIO_RESET_I2C1 1 12*4882a593Smuzhiyun #define PISTACHIO_RESET_I2C2 2 13*4882a593Smuzhiyun #define PISTACHIO_RESET_I2C3 3 14*4882a593Smuzhiyun #define PISTACHIO_RESET_I2S_IN 4 15*4882a593Smuzhiyun #define PISTACHIO_RESET_PRL_OUT 5 16*4882a593Smuzhiyun #define PISTACHIO_RESET_SPDIF_OUT 6 17*4882a593Smuzhiyun #define PISTACHIO_RESET_SPI 7 18*4882a593Smuzhiyun #define PISTACHIO_RESET_PWM_PDM 8 19*4882a593Smuzhiyun #define PISTACHIO_RESET_UART0 9 20*4882a593Smuzhiyun #define PISTACHIO_RESET_UART1 10 21*4882a593Smuzhiyun #define PISTACHIO_RESET_QSPI 11 22*4882a593Smuzhiyun #define PISTACHIO_RESET_MDC 12 23*4882a593Smuzhiyun #define PISTACHIO_RESET_SDHOST 13 24*4882a593Smuzhiyun #define PISTACHIO_RESET_ETHERNET 14 25*4882a593Smuzhiyun #define PISTACHIO_RESET_IR 15 26*4882a593Smuzhiyun #define PISTACHIO_RESET_HASH 16 27*4882a593Smuzhiyun #define PISTACHIO_RESET_TIMER 17 28*4882a593Smuzhiyun #define PISTACHIO_RESET_I2S_OUT 18 29*4882a593Smuzhiyun #define PISTACHIO_RESET_SPDIF_IN 19 30*4882a593Smuzhiyun #define PISTACHIO_RESET_EVT 20 31*4882a593Smuzhiyun #define PISTACHIO_RESET_USB_H 21 32*4882a593Smuzhiyun #define PISTACHIO_RESET_USB_PR 22 33*4882a593Smuzhiyun #define PISTACHIO_RESET_USB_PHY_PR 23 34*4882a593Smuzhiyun #define PISTACHIO_RESET_USB_PHY_PON 24 35*4882a593Smuzhiyun #define PISTACHIO_RESET_MAX 24 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38