1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef DT_RESET_OXSEMI_OX820_H 7*4882a593Smuzhiyun #define DT_RESET_OXSEMI_OX820_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RESET_SCU 0 10*4882a593Smuzhiyun #define RESET_LEON 1 11*4882a593Smuzhiyun #define RESET_ARM0 2 12*4882a593Smuzhiyun #define RESET_ARM1 3 13*4882a593Smuzhiyun #define RESET_USBHS 4 14*4882a593Smuzhiyun #define RESET_USBPHYA 5 15*4882a593Smuzhiyun #define RESET_MAC 6 16*4882a593Smuzhiyun #define RESET_PCIEA 7 17*4882a593Smuzhiyun #define RESET_SGDMA 8 18*4882a593Smuzhiyun #define RESET_CIPHER 9 19*4882a593Smuzhiyun #define RESET_DDR 10 20*4882a593Smuzhiyun #define RESET_SATA 11 21*4882a593Smuzhiyun #define RESET_SATA_LINK 12 22*4882a593Smuzhiyun #define RESET_SATA_PHY 13 23*4882a593Smuzhiyun #define RESET_PCIEPHY 14 24*4882a593Smuzhiyun #define RESET_NAND 15 25*4882a593Smuzhiyun #define RESET_GPIO 16 26*4882a593Smuzhiyun #define RESET_UART1 17 27*4882a593Smuzhiyun #define RESET_UART2 18 28*4882a593Smuzhiyun #define RESET_MISC 19 29*4882a593Smuzhiyun #define RESET_I2S 20 30*4882a593Smuzhiyun #define RESET_SD 21 31*4882a593Smuzhiyun #define RESET_MAC_2 22 32*4882a593Smuzhiyun #define RESET_PCIEB 23 33*4882a593Smuzhiyun #define RESET_VIDEO 24 34*4882a593Smuzhiyun #define RESET_DDR_PHY 25 35*4882a593Smuzhiyun #define RESET_USBPHYB 26 36*4882a593Smuzhiyun #define RESET_USBDEV 27 37*4882a593Smuzhiyun /* Reserved 29 */ 38*4882a593Smuzhiyun #define RESET_ARMDBG 29 39*4882a593Smuzhiyun #define RESET_PLLA 30 40*4882a593Smuzhiyun #define RESET_PLLB 31 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* DT_RESET_OXSEMI_OX820_H */ 43