1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun // Copyright (c) 2019 Nuvoton Technology corporation. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _DT_BINDINGS_NPCM7XX_RESET_H 5*4882a593Smuzhiyun #define _DT_BINDINGS_NPCM7XX_RESET_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define NPCM7XX_RESET_IPSRST1 0x20 8*4882a593Smuzhiyun #define NPCM7XX_RESET_IPSRST2 0x24 9*4882a593Smuzhiyun #define NPCM7XX_RESET_IPSRST3 0x34 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ 12*4882a593Smuzhiyun #define NPCM7XX_RESET_FIU3 1 13*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC1 5 14*4882a593Smuzhiyun #define NPCM7XX_RESET_EMC1 6 15*4882a593Smuzhiyun #define NPCM7XX_RESET_UART_2_3 7 16*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC2 8 17*4882a593Smuzhiyun #define NPCM7XX_RESET_PECI 9 18*4882a593Smuzhiyun #define NPCM7XX_RESET_AES 10 19*4882a593Smuzhiyun #define NPCM7XX_RESET_UART_0_1 11 20*4882a593Smuzhiyun #define NPCM7XX_RESET_MC 12 21*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB2 13 22*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB3 14 23*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB4 15 24*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB5 16 25*4882a593Smuzhiyun #define NPCM7XX_RESET_PWM_M0 18 26*4882a593Smuzhiyun #define NPCM7XX_RESET_TIMER_0_4 19 27*4882a593Smuzhiyun #define NPCM7XX_RESET_TIMER_5_9 20 28*4882a593Smuzhiyun #define NPCM7XX_RESET_EMC2 21 29*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC4 22 30*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC5 23 31*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC6 24 32*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC3 25 33*4882a593Smuzhiyun #define NPCM7XX_RESET_ADC 27 34*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB6 28 35*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB7 29 36*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB0 30 37*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB1 31 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ 40*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT0 0 41*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT1 1 42*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT2 2 43*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT3 3 44*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT4 4 45*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT5 5 46*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT6 6 47*4882a593Smuzhiyun #define NPCM7XX_RESET_MFT7 7 48*4882a593Smuzhiyun #define NPCM7XX_RESET_MMC 8 49*4882a593Smuzhiyun #define NPCM7XX_RESET_SDHC 9 50*4882a593Smuzhiyun #define NPCM7XX_RESET_GFX_SYS 10 51*4882a593Smuzhiyun #define NPCM7XX_RESET_AHB_PCIBRG 11 52*4882a593Smuzhiyun #define NPCM7XX_RESET_VDMA 12 53*4882a593Smuzhiyun #define NPCM7XX_RESET_ECE 13 54*4882a593Smuzhiyun #define NPCM7XX_RESET_VCD 14 55*4882a593Smuzhiyun #define NPCM7XX_RESET_OTP 16 56*4882a593Smuzhiyun #define NPCM7XX_RESET_SIOX1 18 57*4882a593Smuzhiyun #define NPCM7XX_RESET_SIOX2 19 58*4882a593Smuzhiyun #define NPCM7XX_RESET_3DES 21 59*4882a593Smuzhiyun #define NPCM7XX_RESET_PSPI1 22 60*4882a593Smuzhiyun #define NPCM7XX_RESET_PSPI2 23 61*4882a593Smuzhiyun #define NPCM7XX_RESET_GMAC2 25 62*4882a593Smuzhiyun #define NPCM7XX_RESET_USB_HOST 26 63*4882a593Smuzhiyun #define NPCM7XX_RESET_GMAC1 28 64*4882a593Smuzhiyun #define NPCM7XX_RESET_CP 31 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ 67*4882a593Smuzhiyun #define NPCM7XX_RESET_PWM_M1 0 68*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB12 1 69*4882a593Smuzhiyun #define NPCM7XX_RESET_SPIX 2 70*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB13 3 71*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC0 4 72*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC7 5 73*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC8 6 74*4882a593Smuzhiyun #define NPCM7XX_RESET_UDC9 7 75*4882a593Smuzhiyun #define NPCM7XX_RESET_PCI_MAILBOX 9 76*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB14 12 77*4882a593Smuzhiyun #define NPCM7XX_RESET_SHA 13 78*4882a593Smuzhiyun #define NPCM7XX_RESET_SEC_ECC 14 79*4882a593Smuzhiyun #define NPCM7XX_RESET_PCIE_RC 15 80*4882a593Smuzhiyun #define NPCM7XX_RESET_TIMER_10_14 16 81*4882a593Smuzhiyun #define NPCM7XX_RESET_RNG 17 82*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB15 18 83*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB8 19 84*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB9 20 85*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB10 21 86*4882a593Smuzhiyun #define NPCM7XX_RESET_SMB11 22 87*4882a593Smuzhiyun #define NPCM7XX_RESET_ESPI 23 88*4882a593Smuzhiyun #define NPCM7XX_RESET_USB_PHY_1 24 89*4882a593Smuzhiyun #define NPCM7XX_RESET_USB_PHY_2 25 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif 92