1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Flora Fu, MediaTek 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 8*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_MT8173 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* INFRACFG resets */ 11*4882a593Smuzhiyun #define MT8173_INFRA_EMI_REG_RST 0 12*4882a593Smuzhiyun #define MT8173_INFRA_DRAMC0_A0_RST 1 13*4882a593Smuzhiyun #define MT8173_INFRA_APCIRQ_EINT_RST 3 14*4882a593Smuzhiyun #define MT8173_INFRA_APXGPT_RST 4 15*4882a593Smuzhiyun #define MT8173_INFRA_SCPSYS_RST 5 16*4882a593Smuzhiyun #define MT8173_INFRA_KP_RST 6 17*4882a593Smuzhiyun #define MT8173_INFRA_PMIC_WRAP_RST 7 18*4882a593Smuzhiyun #define MT8173_INFRA_MPIP_RST 8 19*4882a593Smuzhiyun #define MT8173_INFRA_CEC_RST 9 20*4882a593Smuzhiyun #define MT8173_INFRA_EMI_RST 32 21*4882a593Smuzhiyun #define MT8173_INFRA_DRAMC0_RST 34 22*4882a593Smuzhiyun #define MT8173_INFRA_APMIXEDSYS_RST 35 23*4882a593Smuzhiyun #define MT8173_INFRA_MIPI_DSI_RST 36 24*4882a593Smuzhiyun #define MT8173_INFRA_TRNG_RST 37 25*4882a593Smuzhiyun #define MT8173_INFRA_SYSIRQ_RST 38 26*4882a593Smuzhiyun #define MT8173_INFRA_MIPI_CSI_RST 39 27*4882a593Smuzhiyun #define MT8173_INFRA_GCE_FAXI_RST 40 28*4882a593Smuzhiyun #define MT8173_INFRA_MMIOMMURST 47 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* PERICFG resets */ 32*4882a593Smuzhiyun #define MT8173_PERI_UART0_SW_RST 0 33*4882a593Smuzhiyun #define MT8173_PERI_UART1_SW_RST 1 34*4882a593Smuzhiyun #define MT8173_PERI_UART2_SW_RST 2 35*4882a593Smuzhiyun #define MT8173_PERI_UART3_SW_RST 3 36*4882a593Smuzhiyun #define MT8173_PERI_IRRX_SW_RST 4 37*4882a593Smuzhiyun #define MT8173_PERI_PWM_SW_RST 8 38*4882a593Smuzhiyun #define MT8173_PERI_AUXADC_SW_RST 10 39*4882a593Smuzhiyun #define MT8173_PERI_DMA_SW_RST 11 40*4882a593Smuzhiyun #define MT8173_PERI_I2C6_SW_RST 13 41*4882a593Smuzhiyun #define MT8173_PERI_NFI_SW_RST 14 42*4882a593Smuzhiyun #define MT8173_PERI_THERM_SW_RST 16 43*4882a593Smuzhiyun #define MT8173_PERI_MSDC2_SW_RST 17 44*4882a593Smuzhiyun #define MT8173_PERI_MSDC3_SW_RST 18 45*4882a593Smuzhiyun #define MT8173_PERI_MSDC0_SW_RST 19 46*4882a593Smuzhiyun #define MT8173_PERI_MSDC1_SW_RST 20 47*4882a593Smuzhiyun #define MT8173_PERI_I2C0_SW_RST 22 48*4882a593Smuzhiyun #define MT8173_PERI_I2C1_SW_RST 23 49*4882a593Smuzhiyun #define MT8173_PERI_I2C2_SW_RST 24 50*4882a593Smuzhiyun #define MT8173_PERI_I2C3_SW_RST 25 51*4882a593Smuzhiyun #define MT8173_PERI_I2C4_SW_RST 26 52*4882a593Smuzhiyun #define MT8173_PERI_HDMI_SW_RST 29 53*4882a593Smuzhiyun #define MT8173_PERI_SPI0_SW_RST 33 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ 56