1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019 MediaTek Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_MT7629 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* INFRACFG resets */ 10*4882a593Smuzhiyun #define MT7629_INFRA_EMI_MPU_RST 0 11*4882a593Smuzhiyun #define MT7629_INFRA_UART5_RST 2 12*4882a593Smuzhiyun #define MT7629_INFRA_CIRQ_EINT_RST 3 13*4882a593Smuzhiyun #define MT7629_INFRA_APXGPT_RST 4 14*4882a593Smuzhiyun #define MT7629_INFRA_SCPSYS_RST 5 15*4882a593Smuzhiyun #define MT7629_INFRA_KP_RST 6 16*4882a593Smuzhiyun #define MT7629_INFRA_SPI1_RST 7 17*4882a593Smuzhiyun #define MT7629_INFRA_SPI4_RST 8 18*4882a593Smuzhiyun #define MT7629_INFRA_SYSTIMER_RST 9 19*4882a593Smuzhiyun #define MT7629_INFRA_IRRX_RST 10 20*4882a593Smuzhiyun #define MT7629_INFRA_AO_BUS_RST 16 21*4882a593Smuzhiyun #define MT7629_INFRA_EMI_RST 32 22*4882a593Smuzhiyun #define MT7629_INFRA_APMIXED_RST 35 23*4882a593Smuzhiyun #define MT7629_INFRA_MIPI_RST 36 24*4882a593Smuzhiyun #define MT7629_INFRA_TRNG_RST 37 25*4882a593Smuzhiyun #define MT7629_INFRA_SYSCIRQ_RST 38 26*4882a593Smuzhiyun #define MT7629_INFRA_MIPI_CSI_RST 39 27*4882a593Smuzhiyun #define MT7629_INFRA_GCE_FAXI_RST 40 28*4882a593Smuzhiyun #define MT7629_INFRA_I2C_SRAM_RST 41 29*4882a593Smuzhiyun #define MT7629_INFRA_IOMMU_RST 47 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* PERICFG resets */ 32*4882a593Smuzhiyun #define MT7629_PERI_UART0_SW_RST 0 33*4882a593Smuzhiyun #define MT7629_PERI_UART1_SW_RST 1 34*4882a593Smuzhiyun #define MT7629_PERI_UART2_SW_RST 2 35*4882a593Smuzhiyun #define MT7629_PERI_BTIF_SW_RST 6 36*4882a593Smuzhiyun #define MT7629_PERI_PWN_SW_RST 8 37*4882a593Smuzhiyun #define MT7629_PERI_DMA_SW_RST 11 38*4882a593Smuzhiyun #define MT7629_PERI_NFI_SW_RST 14 39*4882a593Smuzhiyun #define MT7629_PERI_I2C0_SW_RST 22 40*4882a593Smuzhiyun #define MT7629_PERI_SPI0_SW_RST 33 41*4882a593Smuzhiyun #define MT7629_PERI_SPI1_SW_RST 34 42*4882a593Smuzhiyun #define MT7629_PERI_FLASHIF_SW_RST 36 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* PCIe Subsystem resets */ 45*4882a593Smuzhiyun #define MT7629_PCIE1_CORE_RST 19 46*4882a593Smuzhiyun #define MT7629_PCIE1_MMIO_RST 20 47*4882a593Smuzhiyun #define MT7629_PCIE1_HRST 21 48*4882a593Smuzhiyun #define MT7629_PCIE1_USER_RST 22 49*4882a593Smuzhiyun #define MT7629_PCIE1_PIPE_RST 23 50*4882a593Smuzhiyun #define MT7629_PCIE0_CORE_RST 27 51*4882a593Smuzhiyun #define MT7629_PCIE0_MMIO_RST 28 52*4882a593Smuzhiyun #define MT7629_PCIE0_HRST 29 53*4882a593Smuzhiyun #define MT7629_PCIE0_USER_RST 30 54*4882a593Smuzhiyun #define MT7629_PCIE0_PIPE_RST 31 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* SSUSB Subsystem resets */ 57*4882a593Smuzhiyun #define MT7629_SSUSB_PHY_PWR_RST 3 58*4882a593Smuzhiyun #define MT7629_SSUSB_MAC_PWR_RST 4 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* ETH Subsystem resets */ 61*4882a593Smuzhiyun #define MT7629_ETHSYS_SYS_RST 0 62*4882a593Smuzhiyun #define MT7629_ETHSYS_MCM_RST 2 63*4882a593Smuzhiyun #define MT7629_ETHSYS_HSDMA_RST 5 64*4882a593Smuzhiyun #define MT7629_ETHSYS_FE_RST 6 65*4882a593Smuzhiyun #define MT7629_ETHSYS_ESW_RST 16 66*4882a593Smuzhiyun #define MT7629_ETHSYS_GMAC_RST 23 67*4882a593Smuzhiyun #define MT7629_ETHSYS_EPHY_RST 24 68*4882a593Smuzhiyun #define MT7629_ETHSYS_CRYPTO_RST 29 69*4882a593Smuzhiyun #define MT7629_ETHSYS_PPE_RST 31 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */ 72