1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Sean Wang <sean.wang@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 8*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_MT7622 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* INFRACFG resets */ 11*4882a593Smuzhiyun #define MT7622_INFRA_EMI_REG_RST 0 12*4882a593Smuzhiyun #define MT7622_INFRA_DRAMC0_A0_RST 1 13*4882a593Smuzhiyun #define MT7622_INFRA_APCIRQ_EINT_RST 3 14*4882a593Smuzhiyun #define MT7622_INFRA_APXGPT_RST 4 15*4882a593Smuzhiyun #define MT7622_INFRA_SCPSYS_RST 5 16*4882a593Smuzhiyun #define MT7622_INFRA_PMIC_WRAP_RST 7 17*4882a593Smuzhiyun #define MT7622_INFRA_IRRX_RST 9 18*4882a593Smuzhiyun #define MT7622_INFRA_EMI_RST 16 19*4882a593Smuzhiyun #define MT7622_INFRA_WED0_RST 17 20*4882a593Smuzhiyun #define MT7622_INFRA_DRAMC_RST 18 21*4882a593Smuzhiyun #define MT7622_INFRA_CCI_INTF_RST 19 22*4882a593Smuzhiyun #define MT7622_INFRA_TRNG_RST 21 23*4882a593Smuzhiyun #define MT7622_INFRA_SYSIRQ_RST 22 24*4882a593Smuzhiyun #define MT7622_INFRA_WED1_RST 25 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* PERICFG Subsystem resets */ 27*4882a593Smuzhiyun #define MT7622_PERI_UART0_SW_RST 0 28*4882a593Smuzhiyun #define MT7622_PERI_UART1_SW_RST 1 29*4882a593Smuzhiyun #define MT7622_PERI_UART2_SW_RST 2 30*4882a593Smuzhiyun #define MT7622_PERI_UART3_SW_RST 3 31*4882a593Smuzhiyun #define MT7622_PERI_UART4_SW_RST 4 32*4882a593Smuzhiyun #define MT7622_PERI_BTIF_SW_RST 6 33*4882a593Smuzhiyun #define MT7622_PERI_PWM_SW_RST 8 34*4882a593Smuzhiyun #define MT7622_PERI_AUXADC_SW_RST 10 35*4882a593Smuzhiyun #define MT7622_PERI_DMA_SW_RST 11 36*4882a593Smuzhiyun #define MT7622_PERI_IRTX_SW_RST 13 37*4882a593Smuzhiyun #define MT7622_PERI_NFI_SW_RST 14 38*4882a593Smuzhiyun #define MT7622_PERI_THERM_SW_RST 16 39*4882a593Smuzhiyun #define MT7622_PERI_MSDC0_SW_RST 19 40*4882a593Smuzhiyun #define MT7622_PERI_MSDC1_SW_RST 20 41*4882a593Smuzhiyun #define MT7622_PERI_I2C0_SW_RST 22 42*4882a593Smuzhiyun #define MT7622_PERI_I2C1_SW_RST 23 43*4882a593Smuzhiyun #define MT7622_PERI_I2C2_SW_RST 24 44*4882a593Smuzhiyun #define MT7622_PERI_SPI0_SW_RST 33 45*4882a593Smuzhiyun #define MT7622_PERI_SPI1_SW_RST 34 46*4882a593Smuzhiyun #define MT7622_PERI_FLASHIF_SW_RST 36 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* TOPRGU resets */ 49*4882a593Smuzhiyun #define MT7622_TOPRGU_INFRA_RST 0 50*4882a593Smuzhiyun #define MT7622_TOPRGU_ETHDMA_RST 1 51*4882a593Smuzhiyun #define MT7622_TOPRGU_DDRPHY_RST 6 52*4882a593Smuzhiyun #define MT7622_TOPRGU_INFRA_AO_RST 8 53*4882a593Smuzhiyun #define MT7622_TOPRGU_CONN_RST 9 54*4882a593Smuzhiyun #define MT7622_TOPRGU_APMIXED_RST 10 55*4882a593Smuzhiyun #define MT7622_TOPRGU_CONN_MCU_RST 12 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* PCIe/SATA Subsystem resets */ 58*4882a593Smuzhiyun #define MT7622_SATA_PHY_REG_RST 12 59*4882a593Smuzhiyun #define MT7622_SATA_PHY_SW_RST 13 60*4882a593Smuzhiyun #define MT7622_SATA_AXI_BUS_RST 15 61*4882a593Smuzhiyun #define MT7622_PCIE1_CORE_RST 19 62*4882a593Smuzhiyun #define MT7622_PCIE1_MMIO_RST 20 63*4882a593Smuzhiyun #define MT7622_PCIE1_HRST 21 64*4882a593Smuzhiyun #define MT7622_PCIE1_USER_RST 22 65*4882a593Smuzhiyun #define MT7622_PCIE1_PIPE_RST 23 66*4882a593Smuzhiyun #define MT7622_PCIE0_CORE_RST 27 67*4882a593Smuzhiyun #define MT7622_PCIE0_MMIO_RST 28 68*4882a593Smuzhiyun #define MT7622_PCIE0_HRST 29 69*4882a593Smuzhiyun #define MT7622_PCIE0_USER_RST 30 70*4882a593Smuzhiyun #define MT7622_PCIE0_PIPE_RST 31 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* SSUSB Subsystem resets */ 73*4882a593Smuzhiyun #define MT7622_SSUSB_PHY_PWR_RST 3 74*4882a593Smuzhiyun #define MT7622_SSUSB_MAC_PWR_RST 4 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* ETHSYS Subsystem resets */ 77*4882a593Smuzhiyun #define MT7622_ETHSYS_SYS_RST 0 78*4882a593Smuzhiyun #define MT7622_ETHSYS_MCM_RST 2 79*4882a593Smuzhiyun #define MT7622_ETHSYS_HSDMA_RST 5 80*4882a593Smuzhiyun #define MT7622_ETHSYS_FE_RST 6 81*4882a593Smuzhiyun #define MT7622_ETHSYS_GMAC_RST 23 82*4882a593Smuzhiyun #define MT7622_ETHSYS_EPHY_RST 24 83*4882a593Smuzhiyun #define MT7622_ETHSYS_CRYPTO_RST 29 84*4882a593Smuzhiyun #define MT7622_ETHSYS_PPE_RST 31 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ 87