1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_MT2701 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* INFRACFG resets */ 10*4882a593Smuzhiyun #define MT2701_INFRA_EMI_REG_RST 0 11*4882a593Smuzhiyun #define MT2701_INFRA_DRAMC0_A0_RST 1 12*4882a593Smuzhiyun #define MT2701_INFRA_FHCTL_RST 2 13*4882a593Smuzhiyun #define MT2701_INFRA_APCIRQ_EINT_RST 3 14*4882a593Smuzhiyun #define MT2701_INFRA_APXGPT_RST 4 15*4882a593Smuzhiyun #define MT2701_INFRA_SCPSYS_RST 5 16*4882a593Smuzhiyun #define MT2701_INFRA_KP_RST 6 17*4882a593Smuzhiyun #define MT2701_INFRA_PMIC_WRAP_RST 7 18*4882a593Smuzhiyun #define MT2701_INFRA_MIPI_RST 8 19*4882a593Smuzhiyun #define MT2701_INFRA_IRRX_RST 9 20*4882a593Smuzhiyun #define MT2701_INFRA_CEC_RST 10 21*4882a593Smuzhiyun #define MT2701_INFRA_EMI_RST 32 22*4882a593Smuzhiyun #define MT2701_INFRA_DRAMC0_RST 34 23*4882a593Smuzhiyun #define MT2701_INFRA_TRNG_RST 37 24*4882a593Smuzhiyun #define MT2701_INFRA_SYSIRQ_RST 38 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* PERICFG resets */ 27*4882a593Smuzhiyun #define MT2701_PERI_UART0_SW_RST 0 28*4882a593Smuzhiyun #define MT2701_PERI_UART1_SW_RST 1 29*4882a593Smuzhiyun #define MT2701_PERI_UART2_SW_RST 2 30*4882a593Smuzhiyun #define MT2701_PERI_UART3_SW_RST 3 31*4882a593Smuzhiyun #define MT2701_PERI_GCPU_SW_RST 5 32*4882a593Smuzhiyun #define MT2701_PERI_BTIF_SW_RST 6 33*4882a593Smuzhiyun #define MT2701_PERI_PWM_SW_RST 8 34*4882a593Smuzhiyun #define MT2701_PERI_AUXADC_SW_RST 10 35*4882a593Smuzhiyun #define MT2701_PERI_DMA_SW_RST 11 36*4882a593Smuzhiyun #define MT2701_PERI_NFI_SW_RST 14 37*4882a593Smuzhiyun #define MT2701_PERI_NLI_SW_RST 15 38*4882a593Smuzhiyun #define MT2701_PERI_THERM_SW_RST 16 39*4882a593Smuzhiyun #define MT2701_PERI_MSDC2_SW_RST 17 40*4882a593Smuzhiyun #define MT2701_PERI_MSDC0_SW_RST 19 41*4882a593Smuzhiyun #define MT2701_PERI_MSDC1_SW_RST 20 42*4882a593Smuzhiyun #define MT2701_PERI_I2C0_SW_RST 22 43*4882a593Smuzhiyun #define MT2701_PERI_I2C1_SW_RST 23 44*4882a593Smuzhiyun #define MT2701_PERI_I2C2_SW_RST 24 45*4882a593Smuzhiyun #define MT2701_PERI_I2C3_SW_RST 25 46*4882a593Smuzhiyun #define MT2701_PERI_USB_SW_RST 28 47*4882a593Smuzhiyun #define MT2701_PERI_ETH_SW_RST 29 48*4882a593Smuzhiyun #define MT2701_PERI_SPI0_SW_RST 33 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* TOPRGU resets */ 51*4882a593Smuzhiyun #define MT2701_TOPRGU_INFRA_RST 0 52*4882a593Smuzhiyun #define MT2701_TOPRGU_MM_RST 1 53*4882a593Smuzhiyun #define MT2701_TOPRGU_MFG_RST 2 54*4882a593Smuzhiyun #define MT2701_TOPRGU_ETHDMA_RST 3 55*4882a593Smuzhiyun #define MT2701_TOPRGU_VDEC_RST 4 56*4882a593Smuzhiyun #define MT2701_TOPRGU_VENC_IMG_RST 5 57*4882a593Smuzhiyun #define MT2701_TOPRGU_DDRPHY_RST 6 58*4882a593Smuzhiyun #define MT2701_TOPRGU_MD_RST 7 59*4882a593Smuzhiyun #define MT2701_TOPRGU_INFRA_AO_RST 8 60*4882a593Smuzhiyun #define MT2701_TOPRGU_CONN_RST 9 61*4882a593Smuzhiyun #define MT2701_TOPRGU_APMIXED_RST 10 62*4882a593Smuzhiyun #define MT2701_TOPRGU_HIFSYS_RST 11 63*4882a593Smuzhiyun #define MT2701_TOPRGU_CONN_MCU_RST 12 64*4882a593Smuzhiyun #define MT2701_TOPRGU_BDP_DISP_RST 13 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* HIFSYS resets */ 67*4882a593Smuzhiyun #define MT2701_HIFSYS_UHOST0_RST 3 68*4882a593Smuzhiyun #define MT2701_HIFSYS_UHOST1_RST 4 69*4882a593Smuzhiyun #define MT2701_HIFSYS_UPHY0_RST 21 70*4882a593Smuzhiyun #define MT2701_HIFSYS_UPHY1_RST 22 71*4882a593Smuzhiyun #define MT2701_HIFSYS_PCIE0_RST 24 72*4882a593Smuzhiyun #define MT2701_HIFSYS_PCIE1_RST 25 73*4882a593Smuzhiyun #define MT2701_HIFSYS_PCIE2_RST 26 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* ETHSYS resets */ 76*4882a593Smuzhiyun #define MT2701_ETHSYS_SYS_RST 0 77*4882a593Smuzhiyun #define MT2701_ETHSYS_MCM_RST 2 78*4882a593Smuzhiyun #define MT2701_ETHSYS_FE_RST 6 79*4882a593Smuzhiyun #define MT2701_ETHSYS_GMAC_RST 23 80*4882a593Smuzhiyun #define MT2701_ETHSYS_PPE_RST 31 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* G3DSYS resets */ 83*4882a593Smuzhiyun #define MT2701_G3DSYS_CORE_RST 0 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ 86