1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Zodiac Inflight Innovations 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef DT_BINDING_RESET_IMX8MQ_H 9*4882a593Smuzhiyun #define DT_BINDING_RESET_IMX8MQ_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 12*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 13*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 14*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 15*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_RESET0 4 16*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_RESET1 5 17*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_RESET2 6 18*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_CORE_RESET3 7 19*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_DBG_RESET0 8 20*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_DBG_RESET1 9 21*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_DBG_RESET2 10 22*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_DBG_RESET3 11 23*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_ETM_RESET0 12 24*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_ETM_RESET1 13 25*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_ETM_RESET2 14 26*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_ETM_RESET3 15 27*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 28*4882a593Smuzhiyun #define IMX8MQ_RESET_A53_L2RESET 17 29*4882a593Smuzhiyun #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 30*4882a593Smuzhiyun #define IMX8MQ_RESET_OTG1_PHY_RESET 19 31*4882a593Smuzhiyun #define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ 32*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ 33*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ 34*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ 35*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ 36*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ 37*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ 38*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ 39*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ 40*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ 41*4882a593Smuzhiyun #define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ 42*4882a593Smuzhiyun #define IMX8MQ_RESET_DISP_RESET 31 43*4882a593Smuzhiyun #define IMX8MQ_RESET_GPU_RESET 32 44*4882a593Smuzhiyun #define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ 45*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ 46*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ 47*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ 48*4882a593Smuzhiyun #define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ 49*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ 50*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ 51*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ 52*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ 53*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ 54*4882a593Smuzhiyun #define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ 55*4882a593Smuzhiyun #define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ 56*4882a593Smuzhiyun #define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ 57*4882a593Smuzhiyun #define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ 58*4882a593Smuzhiyun #define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ 59*4882a593Smuzhiyun #define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ 60*4882a593Smuzhiyun #define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ 61*4882a593Smuzhiyun #define IMX8MQ_RESET_SW_M4C_RST 50 62*4882a593Smuzhiyun #define IMX8MQ_RESET_SW_M4P_RST 51 63*4882a593Smuzhiyun #define IMX8MQ_RESET_M4_ENABLE 52 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define IMX8MQ_RESET_NUM 53 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68