1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /** 3*4882a593Smuzhiyun * This header provides index for the reset controller 4*4882a593Smuzhiyun * based on hi6220 SoC. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define PERIPH_RSTDIS0_MMC0 0x000 10*4882a593Smuzhiyun #define PERIPH_RSTDIS0_MMC1 0x001 11*4882a593Smuzhiyun #define PERIPH_RSTDIS0_MMC2 0x002 12*4882a593Smuzhiyun #define PERIPH_RSTDIS0_NANDC 0x003 13*4882a593Smuzhiyun #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 14*4882a593Smuzhiyun #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 15*4882a593Smuzhiyun #define PERIPH_RSTDIS0_USBOTG 0x006 16*4882a593Smuzhiyun #define PERIPH_RSTDIS0_USBOTG_32K 0x007 17*4882a593Smuzhiyun #define PERIPH_RSTDIS1_HIFI 0x100 18*4882a593Smuzhiyun #define PERIPH_RSTDIS1_DIGACODEC 0x105 19*4882a593Smuzhiyun #define PERIPH_RSTEN2_IPF 0x200 20*4882a593Smuzhiyun #define PERIPH_RSTEN2_SOCP 0x201 21*4882a593Smuzhiyun #define PERIPH_RSTEN2_DMAC 0x202 22*4882a593Smuzhiyun #define PERIPH_RSTEN2_SECENG 0x203 23*4882a593Smuzhiyun #define PERIPH_RSTEN2_ABB 0x204 24*4882a593Smuzhiyun #define PERIPH_RSTEN2_HPM0 0x205 25*4882a593Smuzhiyun #define PERIPH_RSTEN2_HPM1 0x206 26*4882a593Smuzhiyun #define PERIPH_RSTEN2_HPM2 0x207 27*4882a593Smuzhiyun #define PERIPH_RSTEN2_HPM3 0x208 28*4882a593Smuzhiyun #define PERIPH_RSTEN3_CSSYS 0x300 29*4882a593Smuzhiyun #define PERIPH_RSTEN3_I2C0 0x301 30*4882a593Smuzhiyun #define PERIPH_RSTEN3_I2C1 0x302 31*4882a593Smuzhiyun #define PERIPH_RSTEN3_I2C2 0x303 32*4882a593Smuzhiyun #define PERIPH_RSTEN3_I2C3 0x304 33*4882a593Smuzhiyun #define PERIPH_RSTEN3_UART1 0x305 34*4882a593Smuzhiyun #define PERIPH_RSTEN3_UART2 0x306 35*4882a593Smuzhiyun #define PERIPH_RSTEN3_UART3 0x307 36*4882a593Smuzhiyun #define PERIPH_RSTEN3_UART4 0x308 37*4882a593Smuzhiyun #define PERIPH_RSTEN3_SSP 0x309 38*4882a593Smuzhiyun #define PERIPH_RSTEN3_PWM 0x30a 39*4882a593Smuzhiyun #define PERIPH_RSTEN3_BLPWM 0x30b 40*4882a593Smuzhiyun #define PERIPH_RSTEN3_TSENSOR 0x30c 41*4882a593Smuzhiyun #define PERIPH_RSTEN3_DAPB 0x312 42*4882a593Smuzhiyun #define PERIPH_RSTEN3_HKADC 0x313 43*4882a593Smuzhiyun #define PERIPH_RSTEN3_CODEC_SSI 0x314 44*4882a593Smuzhiyun #define PERIPH_RSTEN3_PMUSSI1 0x316 45*4882a593Smuzhiyun #define PERIPH_RSTEN8_RS0 0x400 46*4882a593Smuzhiyun #define PERIPH_RSTEN8_RS2 0x401 47*4882a593Smuzhiyun #define PERIPH_RSTEN8_RS3 0x402 48*4882a593Smuzhiyun #define PERIPH_RSTEN8_MS0 0x403 49*4882a593Smuzhiyun #define PERIPH_RSTEN8_MS2 0x405 50*4882a593Smuzhiyun #define PERIPH_RSTEN8_XG2RAM0 0x406 51*4882a593Smuzhiyun #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 52*4882a593Smuzhiyun #define PERIPH_RSTEN8_SRAM 0x408 53*4882a593Smuzhiyun #define PERIPH_RSTEN8_HARQ 0x40a 54*4882a593Smuzhiyun #define PERIPH_RSTEN8_DDRC 0x40c 55*4882a593Smuzhiyun #define PERIPH_RSTEN8_DDRC_APB 0x40d 56*4882a593Smuzhiyun #define PERIPH_RSTEN8_DDRPACK_APB 0x40e 57*4882a593Smuzhiyun #define PERIPH_RSTEN8_DDRT 0x411 58*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_DAP 0x500 59*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_ATB 0x501 60*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_LBUS 0x502 61*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_POR 0x503 62*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_CORE 0x504 63*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_DBG 0x505 64*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_L2 0x506 65*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 66*4882a593Smuzhiyun #define PERIPH_RSDIST9_CARM_ETM 0x508 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define MEDIA_G3D 0 69*4882a593Smuzhiyun #define MEDIA_CODEC_VPU 2 70*4882a593Smuzhiyun #define MEDIA_CODEC_JPEG 3 71*4882a593Smuzhiyun #define MEDIA_ISP 4 72*4882a593Smuzhiyun #define MEDIA_ADE 5 73*4882a593Smuzhiyun #define MEDIA_MMU 6 74*4882a593Smuzhiyun #define MEDIA_XG2RAM1 7 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define AO_G3D 1 77*4882a593Smuzhiyun #define AO_CODECISP 2 78*4882a593Smuzhiyun #define AO_MCPU 4 79*4882a593Smuzhiyun #define AO_BBPHARQMEM 5 80*4882a593Smuzhiyun #define AO_HIFI 8 81*4882a593Smuzhiyun #define AO_ACPUSCUL2C 12 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 84