1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H 3*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CORTINA_GEMINI_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define GEMINI_RESET_DRAM 0 6*4882a593Smuzhiyun #define GEMINI_RESET_FLASH 1 7*4882a593Smuzhiyun #define GEMINI_RESET_IDE 2 8*4882a593Smuzhiyun #define GEMINI_RESET_RAID 3 9*4882a593Smuzhiyun #define GEMINI_RESET_SECURITY 4 10*4882a593Smuzhiyun #define GEMINI_RESET_GMAC0 5 11*4882a593Smuzhiyun #define GEMINI_RESET_GMAC1 6 12*4882a593Smuzhiyun #define GEMINI_RESET_PCI 7 13*4882a593Smuzhiyun #define GEMINI_RESET_USB0 8 14*4882a593Smuzhiyun #define GEMINI_RESET_USB1 9 15*4882a593Smuzhiyun #define GEMINI_RESET_DMAC 10 16*4882a593Smuzhiyun #define GEMINI_RESET_APB 11 17*4882a593Smuzhiyun #define GEMINI_RESET_LPC 12 18*4882a593Smuzhiyun #define GEMINI_RESET_LCD 13 19*4882a593Smuzhiyun #define GEMINI_RESET_INTCON0 14 20*4882a593Smuzhiyun #define GEMINI_RESET_INTCON1 15 21*4882a593Smuzhiyun #define GEMINI_RESET_RTC 16 22*4882a593Smuzhiyun #define GEMINI_RESET_TIMER 17 23*4882a593Smuzhiyun #define GEMINI_RESET_UART 18 24*4882a593Smuzhiyun #define GEMINI_RESET_SSP 19 25*4882a593Smuzhiyun #define GEMINI_RESET_GPIO0 20 26*4882a593Smuzhiyun #define GEMINI_RESET_GPIO1 21 27*4882a593Smuzhiyun #define GEMINI_RESET_GPIO2 22 28*4882a593Smuzhiyun #define GEMINI_RESET_WDOG 23 29*4882a593Smuzhiyun #define GEMINI_RESET_EXTERN 24 30*4882a593Smuzhiyun #define GEMINI_RESET_CIR 25 31*4882a593Smuzhiyun #define GEMINI_RESET_SATA0 26 32*4882a593Smuzhiyun #define GEMINI_RESET_SATA1 27 33*4882a593Smuzhiyun #define GEMINI_RESET_TVC 28 34*4882a593Smuzhiyun #define GEMINI_RESET_CPU1 30 35*4882a593Smuzhiyun #define GEMINI_RESET_GLOBAL 31 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38