1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Baikal-T1 CCU reset indices 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_RESET_BT1_CCU_H 8*4882a593Smuzhiyun #define __DT_BINDINGS_RESET_BT1_CCU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CCU_AXI_MAIN_RST 0 11*4882a593Smuzhiyun #define CCU_AXI_DDR_RST 1 12*4882a593Smuzhiyun #define CCU_AXI_SATA_RST 2 13*4882a593Smuzhiyun #define CCU_AXI_GMAC0_RST 3 14*4882a593Smuzhiyun #define CCU_AXI_GMAC1_RST 4 15*4882a593Smuzhiyun #define CCU_AXI_XGMAC_RST 5 16*4882a593Smuzhiyun #define CCU_AXI_PCIE_M_RST 6 17*4882a593Smuzhiyun #define CCU_AXI_PCIE_S_RST 7 18*4882a593Smuzhiyun #define CCU_AXI_USB_RST 8 19*4882a593Smuzhiyun #define CCU_AXI_HWA_RST 9 20*4882a593Smuzhiyun #define CCU_AXI_SRAM_RST 10 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CCU_SYS_SATA_REF_RST 0 23*4882a593Smuzhiyun #define CCU_SYS_APB_RST 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ 26