1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 Bitmain Ltd. 4*4882a593Smuzhiyun * Copyright (c) 2019 Linaro Ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_BM1880_RESET_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_BM1880_RESET_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define BM1880_RST_MAIN_AP 0 11*4882a593Smuzhiyun #define BM1880_RST_SECOND_AP 1 12*4882a593Smuzhiyun #define BM1880_RST_DDR 2 13*4882a593Smuzhiyun #define BM1880_RST_VIDEO 3 14*4882a593Smuzhiyun #define BM1880_RST_JPEG 4 15*4882a593Smuzhiyun #define BM1880_RST_VPP 5 16*4882a593Smuzhiyun #define BM1880_RST_GDMA 6 17*4882a593Smuzhiyun #define BM1880_RST_AXI_SRAM 7 18*4882a593Smuzhiyun #define BM1880_RST_TPU 8 19*4882a593Smuzhiyun #define BM1880_RST_USB 9 20*4882a593Smuzhiyun #define BM1880_RST_ETH0 10 21*4882a593Smuzhiyun #define BM1880_RST_ETH1 11 22*4882a593Smuzhiyun #define BM1880_RST_NAND 12 23*4882a593Smuzhiyun #define BM1880_RST_EMMC 13 24*4882a593Smuzhiyun #define BM1880_RST_SD 14 25*4882a593Smuzhiyun #define BM1880_RST_SDMA 15 26*4882a593Smuzhiyun #define BM1880_RST_I2S0 16 27*4882a593Smuzhiyun #define BM1880_RST_I2S1 17 28*4882a593Smuzhiyun #define BM1880_RST_UART0_1_CLK 18 29*4882a593Smuzhiyun #define BM1880_RST_UART0_1_ACLK 19 30*4882a593Smuzhiyun #define BM1880_RST_UART2_3_CLK 20 31*4882a593Smuzhiyun #define BM1880_RST_UART2_3_ACLK 21 32*4882a593Smuzhiyun #define BM1880_RST_MINER 22 33*4882a593Smuzhiyun #define BM1880_RST_I2C0 23 34*4882a593Smuzhiyun #define BM1880_RST_I2C1 24 35*4882a593Smuzhiyun #define BM1880_RST_I2C2 25 36*4882a593Smuzhiyun #define BM1880_RST_I2C3 26 37*4882a593Smuzhiyun #define BM1880_RST_I2C4 27 38*4882a593Smuzhiyun #define BM1880_RST_PWM0 28 39*4882a593Smuzhiyun #define BM1880_RST_PWM1 29 40*4882a593Smuzhiyun #define BM1880_RST_PWM2 30 41*4882a593Smuzhiyun #define BM1880_RST_PWM3 31 42*4882a593Smuzhiyun #define BM1880_RST_SPI 32 43*4882a593Smuzhiyun #define BM1880_RST_GPIO0 33 44*4882a593Smuzhiyun #define BM1880_RST_GPIO1 34 45*4882a593Smuzhiyun #define BM1880_RST_GPIO2 35 46*4882a593Smuzhiyun #define BM1880_RST_EFUSE 36 47*4882a593Smuzhiyun #define BM1880_RST_WDT 37 48*4882a593Smuzhiyun #define BM1880_RST_AHB_ROM 38 49*4882a593Smuzhiyun #define BM1880_RST_SPIC 39 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* _DT_BINDINGS_BM1880_RESET_H */ 52