1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* RESET0 */ 10*4882a593Smuzhiyun #define RESET_HIU 0 11*4882a593Smuzhiyun #define RESET_VLD 1 12*4882a593Smuzhiyun #define RESET_IQIDCT 2 13*4882a593Smuzhiyun #define RESET_MC 3 14*4882a593Smuzhiyun /* 8 */ 15*4882a593Smuzhiyun #define RESET_VIU 5 16*4882a593Smuzhiyun #define RESET_AIU 6 17*4882a593Smuzhiyun #define RESET_MCPU 7 18*4882a593Smuzhiyun #define RESET_CCPU 8 19*4882a593Smuzhiyun #define RESET_PMUX 9 20*4882a593Smuzhiyun #define RESET_VENC 10 21*4882a593Smuzhiyun #define RESET_ASSIST 11 22*4882a593Smuzhiyun #define RESET_AFIFO2 12 23*4882a593Smuzhiyun #define RESET_MDEC 13 24*4882a593Smuzhiyun #define RESET_VLD_PART 14 25*4882a593Smuzhiyun #define RESET_VIFIFO 15 26*4882a593Smuzhiyun /* 16-31 */ 27*4882a593Smuzhiyun /* RESET1 */ 28*4882a593Smuzhiyun /* 32 */ 29*4882a593Smuzhiyun #define RESET_DEMUX 33 30*4882a593Smuzhiyun #define RESET_USB_OTG 34 31*4882a593Smuzhiyun #define RESET_DDR 35 32*4882a593Smuzhiyun #define RESET_VDAC_1 36 33*4882a593Smuzhiyun #define RESET_BT656 37 34*4882a593Smuzhiyun #define RESET_AHB_SRAM 38 35*4882a593Smuzhiyun #define RESET_AHB_BRIDGE 39 36*4882a593Smuzhiyun #define RESET_PARSER 40 37*4882a593Smuzhiyun #define RESET_BLKMV 41 38*4882a593Smuzhiyun #define RESET_ISA 42 39*4882a593Smuzhiyun #define RESET_ETHERNET 43 40*4882a593Smuzhiyun #define RESET_ABUF 44 41*4882a593Smuzhiyun #define RESET_AHB_DATA 45 42*4882a593Smuzhiyun #define RESET_AHB_CNTL 46 43*4882a593Smuzhiyun #define RESET_ROM_BOOT 47 44*4882a593Smuzhiyun /* 48-63 */ 45*4882a593Smuzhiyun /* RESET2 */ 46*4882a593Smuzhiyun #define RESET_VD_RMEM 64 47*4882a593Smuzhiyun #define RESET_AUDIN 65 48*4882a593Smuzhiyun #define RESET_DBLK 66 49*4882a593Smuzhiyun #define RESET_PIC_DC 67 50*4882a593Smuzhiyun #define RESET_PSC 68 51*4882a593Smuzhiyun #define RESET_NAND 69 52*4882a593Smuzhiyun #define RESET_GE2D 70 53*4882a593Smuzhiyun #define RESET_PARSER_REG 71 54*4882a593Smuzhiyun #define RESET_PARSER_FETCH 72 55*4882a593Smuzhiyun #define RESET_PARSER_CTL 73 56*4882a593Smuzhiyun #define RESET_PARSER_TOP 74 57*4882a593Smuzhiyun #define RESET_HDMI_APB 75 58*4882a593Smuzhiyun #define RESET_AUDIO_APB 76 59*4882a593Smuzhiyun #define RESET_MEDIA_CPU 77 60*4882a593Smuzhiyun #define RESET_MALI 78 61*4882a593Smuzhiyun #define RESET_HDMI_SYSTEM_RESET 79 62*4882a593Smuzhiyun /* 80-95 */ 63*4882a593Smuzhiyun /* RESET3 */ 64*4882a593Smuzhiyun #define RESET_RING_OSCILLATOR 96 65*4882a593Smuzhiyun #define RESET_SYS_CPU_0 97 66*4882a593Smuzhiyun #define RESET_EFUSE 98 67*4882a593Smuzhiyun #define RESET_SYS_CPU_BVCI 99 68*4882a593Smuzhiyun #define RESET_AIFIFO 100 69*4882a593Smuzhiyun #define RESET_AUDIO_PLL_MODULATOR 101 70*4882a593Smuzhiyun #define RESET_AHB_BRIDGE_CNTL 102 71*4882a593Smuzhiyun #define RESET_SYS_CPU_1 103 72*4882a593Smuzhiyun #define RESET_AUDIO_DAC 104 73*4882a593Smuzhiyun #define RESET_DEMUX_TOP 105 74*4882a593Smuzhiyun #define RESET_DEMUX_DES 106 75*4882a593Smuzhiyun #define RESET_DEMUX_S2P_0 107 76*4882a593Smuzhiyun #define RESET_DEMUX_S2P_1 108 77*4882a593Smuzhiyun #define RESET_DEMUX_RESET_0 109 78*4882a593Smuzhiyun #define RESET_DEMUX_RESET_1 110 79*4882a593Smuzhiyun #define RESET_DEMUX_RESET_2 111 80*4882a593Smuzhiyun /* 112-127 */ 81*4882a593Smuzhiyun /* RESET4 */ 82*4882a593Smuzhiyun #define RESET_PL310 128 83*4882a593Smuzhiyun #define RESET_A5_APB 129 84*4882a593Smuzhiyun #define RESET_A5_AXI 130 85*4882a593Smuzhiyun #define RESET_A5 131 86*4882a593Smuzhiyun #define RESET_DVIN 132 87*4882a593Smuzhiyun #define RESET_RDMA 133 88*4882a593Smuzhiyun #define RESET_VENCI 134 89*4882a593Smuzhiyun #define RESET_VENCP 135 90*4882a593Smuzhiyun #define RESET_VENCT 136 91*4882a593Smuzhiyun #define RESET_VDAC_4 137 92*4882a593Smuzhiyun #define RESET_RTC 138 93*4882a593Smuzhiyun #define RESET_A5_DEBUG 139 94*4882a593Smuzhiyun #define RESET_VDI6 140 95*4882a593Smuzhiyun #define RESET_VENCL 141 96*4882a593Smuzhiyun /* 142-159 */ 97*4882a593Smuzhiyun /* RESET5 */ 98*4882a593Smuzhiyun #define RESET_DDR_PLL 160 99*4882a593Smuzhiyun #define RESET_MISC_PLL 161 100*4882a593Smuzhiyun #define RESET_SYS_PLL 162 101*4882a593Smuzhiyun #define RESET_HPLL_PLL 163 102*4882a593Smuzhiyun #define RESET_AUDIO_PLL 164 103*4882a593Smuzhiyun #define RESET_VID2_PLL 165 104*4882a593Smuzhiyun /* 166-191 */ 105*4882a593Smuzhiyun /* RESET6 */ 106*4882a593Smuzhiyun #define RESET_PERIPHS_GENERAL 192 107*4882a593Smuzhiyun #define RESET_PERIPHS_IR_REMOTE 193 108*4882a593Smuzhiyun #define RESET_PERIPHS_SMART_CARD 194 109*4882a593Smuzhiyun #define RESET_PERIPHS_SAR_ADC 195 110*4882a593Smuzhiyun #define RESET_PERIPHS_I2C_MASTER_0 196 111*4882a593Smuzhiyun #define RESET_PERIPHS_I2C_MASTER_1 197 112*4882a593Smuzhiyun #define RESET_PERIPHS_I2C_SLAVE 198 113*4882a593Smuzhiyun #define RESET_PERIPHS_STREAM_INTERFACE 199 114*4882a593Smuzhiyun #define RESET_PERIPHS_SDIO 200 115*4882a593Smuzhiyun #define RESET_PERIPHS_UART_0 201 116*4882a593Smuzhiyun #define RESET_PERIPHS_UART_1 202 117*4882a593Smuzhiyun #define RESET_PERIPHS_ASYNC_0 203 118*4882a593Smuzhiyun #define RESET_PERIPHS_ASYNC_1 204 119*4882a593Smuzhiyun #define RESET_PERIPHS_SPI_0 205 120*4882a593Smuzhiyun #define RESET_PERIPHS_SPI_1 206 121*4882a593Smuzhiyun #define RESET_PERIPHS_LED_PWM 207 122*4882a593Smuzhiyun /* 208-223 */ 123*4882a593Smuzhiyun /* RESET7 */ 124*4882a593Smuzhiyun /* 224-255 */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif 127