1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* RESET0 */ 10*4882a593Smuzhiyun #define RESET_HIU 0 11*4882a593Smuzhiyun /* 1 */ 12*4882a593Smuzhiyun #define RESET_DOS_RESET 2 13*4882a593Smuzhiyun #define RESET_DDR_TOP 3 14*4882a593Smuzhiyun #define RESET_DCU_RESET 4 15*4882a593Smuzhiyun #define RESET_VIU 5 16*4882a593Smuzhiyun #define RESET_AIU 6 17*4882a593Smuzhiyun #define RESET_VID_PLL_DIV 7 18*4882a593Smuzhiyun /* 8 */ 19*4882a593Smuzhiyun #define RESET_PMUX 9 20*4882a593Smuzhiyun #define RESET_VENC 10 21*4882a593Smuzhiyun #define RESET_ASSIST 11 22*4882a593Smuzhiyun #define RESET_AFIFO2 12 23*4882a593Smuzhiyun #define RESET_VCBUS 13 24*4882a593Smuzhiyun /* 14 */ 25*4882a593Smuzhiyun /* 15 */ 26*4882a593Smuzhiyun #define RESET_GIC 16 27*4882a593Smuzhiyun #define RESET_CAPB3_DECODE 17 28*4882a593Smuzhiyun #define RESET_NAND_CAPB3 18 29*4882a593Smuzhiyun #define RESET_HDMITX_CAPB3 19 30*4882a593Smuzhiyun #define RESET_MALI_CAPB3 20 31*4882a593Smuzhiyun #define RESET_DOS_CAPB3 21 32*4882a593Smuzhiyun #define RESET_SYS_CPU_CAPB3 22 33*4882a593Smuzhiyun #define RESET_CBUS_CAPB3 23 34*4882a593Smuzhiyun #define RESET_AHB_CNTL 24 35*4882a593Smuzhiyun #define RESET_AHB_DATA 25 36*4882a593Smuzhiyun #define RESET_VCBUS_CLK81 26 37*4882a593Smuzhiyun #define RESET_MMC 27 38*4882a593Smuzhiyun #define RESET_MIPI_0 28 39*4882a593Smuzhiyun #define RESET_MIPI_1 29 40*4882a593Smuzhiyun #define RESET_MIPI_2 30 41*4882a593Smuzhiyun #define RESET_MIPI_3 31 42*4882a593Smuzhiyun /* RESET1 */ 43*4882a593Smuzhiyun #define RESET_CPPM 32 44*4882a593Smuzhiyun #define RESET_DEMUX 33 45*4882a593Smuzhiyun #define RESET_USB_OTG 34 46*4882a593Smuzhiyun #define RESET_DDR 35 47*4882a593Smuzhiyun #define RESET_AO_RESET 36 48*4882a593Smuzhiyun #define RESET_BT656 37 49*4882a593Smuzhiyun #define RESET_AHB_SRAM 38 50*4882a593Smuzhiyun /* 39 */ 51*4882a593Smuzhiyun #define RESET_PARSER 40 52*4882a593Smuzhiyun #define RESET_BLKMV 41 53*4882a593Smuzhiyun #define RESET_ISA 42 54*4882a593Smuzhiyun #define RESET_ETHERNET 43 55*4882a593Smuzhiyun #define RESET_SD_EMMC_A 44 56*4882a593Smuzhiyun #define RESET_SD_EMMC_B 45 57*4882a593Smuzhiyun #define RESET_SD_EMMC_C 46 58*4882a593Smuzhiyun #define RESET_ROM_BOOT 47 59*4882a593Smuzhiyun #define RESET_SYS_CPU_0 48 60*4882a593Smuzhiyun #define RESET_SYS_CPU_1 49 61*4882a593Smuzhiyun #define RESET_SYS_CPU_2 50 62*4882a593Smuzhiyun #define RESET_SYS_CPU_3 51 63*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_0 52 64*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_1 53 65*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_2 54 66*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_3 55 67*4882a593Smuzhiyun #define RESET_SYS_PLL_DIV 56 68*4882a593Smuzhiyun #define RESET_SYS_CPU_AXI 57 69*4882a593Smuzhiyun #define RESET_SYS_CPU_L2 58 70*4882a593Smuzhiyun #define RESET_SYS_CPU_P 59 71*4882a593Smuzhiyun #define RESET_SYS_CPU_MBIST 60 72*4882a593Smuzhiyun #define RESET_ACODEC 61 73*4882a593Smuzhiyun /* 62 */ 74*4882a593Smuzhiyun /* 63 */ 75*4882a593Smuzhiyun /* RESET2 */ 76*4882a593Smuzhiyun #define RESET_VD_RMEM 64 77*4882a593Smuzhiyun #define RESET_AUDIN 65 78*4882a593Smuzhiyun #define RESET_HDMI_TX 66 79*4882a593Smuzhiyun /* 67 */ 80*4882a593Smuzhiyun /* 68 */ 81*4882a593Smuzhiyun /* 69 */ 82*4882a593Smuzhiyun #define RESET_GE2D 70 83*4882a593Smuzhiyun #define RESET_PARSER_REG 71 84*4882a593Smuzhiyun #define RESET_PARSER_FETCH 72 85*4882a593Smuzhiyun #define RESET_PARSER_CTL 73 86*4882a593Smuzhiyun #define RESET_PARSER_TOP 74 87*4882a593Smuzhiyun /* 75 */ 88*4882a593Smuzhiyun /* 76 */ 89*4882a593Smuzhiyun #define RESET_AO_CPU_RESET 77 90*4882a593Smuzhiyun #define RESET_MALI 78 91*4882a593Smuzhiyun #define RESET_HDMI_SYSTEM_RESET 79 92*4882a593Smuzhiyun /* 80-95 */ 93*4882a593Smuzhiyun /* RESET3 */ 94*4882a593Smuzhiyun #define RESET_RING_OSCILLATOR 96 95*4882a593Smuzhiyun #define RESET_SYS_CPU 97 96*4882a593Smuzhiyun #define RESET_EFUSE 98 97*4882a593Smuzhiyun #define RESET_SYS_CPU_BVCI 99 98*4882a593Smuzhiyun #define RESET_AIFIFO 100 99*4882a593Smuzhiyun #define RESET_TVFE 101 100*4882a593Smuzhiyun #define RESET_AHB_BRIDGE_CNTL 102 101*4882a593Smuzhiyun /* 103 */ 102*4882a593Smuzhiyun #define RESET_AUDIO_DAC 104 103*4882a593Smuzhiyun #define RESET_DEMUX_TOP 105 104*4882a593Smuzhiyun #define RESET_DEMUX_DES 106 105*4882a593Smuzhiyun #define RESET_DEMUX_S2P_0 107 106*4882a593Smuzhiyun #define RESET_DEMUX_S2P_1 108 107*4882a593Smuzhiyun #define RESET_DEMUX_RESET_0 109 108*4882a593Smuzhiyun #define RESET_DEMUX_RESET_1 110 109*4882a593Smuzhiyun #define RESET_DEMUX_RESET_2 111 110*4882a593Smuzhiyun /* 112-127 */ 111*4882a593Smuzhiyun /* RESET4 */ 112*4882a593Smuzhiyun /* 128 */ 113*4882a593Smuzhiyun /* 129 */ 114*4882a593Smuzhiyun /* 130 */ 115*4882a593Smuzhiyun /* 131 */ 116*4882a593Smuzhiyun #define RESET_DVIN_RESET 132 117*4882a593Smuzhiyun #define RESET_RDMA 133 118*4882a593Smuzhiyun #define RESET_VENCI 134 119*4882a593Smuzhiyun #define RESET_VENCP 135 120*4882a593Smuzhiyun /* 136 */ 121*4882a593Smuzhiyun #define RESET_VDAC 137 122*4882a593Smuzhiyun #define RESET_RTC 138 123*4882a593Smuzhiyun /* 139 */ 124*4882a593Smuzhiyun #define RESET_VDI6 140 125*4882a593Smuzhiyun #define RESET_VENCL 141 126*4882a593Smuzhiyun #define RESET_I2C_MASTER_2 142 127*4882a593Smuzhiyun #define RESET_I2C_MASTER_1 143 128*4882a593Smuzhiyun /* 144-159 */ 129*4882a593Smuzhiyun /* RESET5 */ 130*4882a593Smuzhiyun /* 160-191 */ 131*4882a593Smuzhiyun /* RESET6 */ 132*4882a593Smuzhiyun #define RESET_PERIPHS_GENERAL 192 133*4882a593Smuzhiyun #define RESET_PERIPHS_SPICC 193 134*4882a593Smuzhiyun #define RESET_PERIPHS_SMART_CARD 194 135*4882a593Smuzhiyun #define RESET_PERIPHS_SAR_ADC 195 136*4882a593Smuzhiyun #define RESET_PERIPHS_I2C_MASTER_0 196 137*4882a593Smuzhiyun #define RESET_SANA 197 138*4882a593Smuzhiyun /* 198 */ 139*4882a593Smuzhiyun #define RESET_PERIPHS_STREAM_INTERFACE 199 140*4882a593Smuzhiyun #define RESET_PERIPHS_SDIO 200 141*4882a593Smuzhiyun #define RESET_PERIPHS_UART_0 201 142*4882a593Smuzhiyun #define RESET_PERIPHS_UART_1_2 202 143*4882a593Smuzhiyun #define RESET_PERIPHS_ASYNC_0 203 144*4882a593Smuzhiyun #define RESET_PERIPHS_ASYNC_1 204 145*4882a593Smuzhiyun #define RESET_PERIPHS_SPI_0 205 146*4882a593Smuzhiyun #define RESET_PERIPHS_SDHC 206 147*4882a593Smuzhiyun #define RESET_UART_SLIP 207 148*4882a593Smuzhiyun /* 208-223 */ 149*4882a593Smuzhiyun /* RESET7 */ 150*4882a593Smuzhiyun #define RESET_USB_DDR_0 224 151*4882a593Smuzhiyun #define RESET_USB_DDR_1 225 152*4882a593Smuzhiyun #define RESET_USB_DDR_2 226 153*4882a593Smuzhiyun #define RESET_USB_DDR_3 227 154*4882a593Smuzhiyun /* 228 */ 155*4882a593Smuzhiyun #define RESET_DEVICE_MMC_ARB 229 156*4882a593Smuzhiyun /* 230 */ 157*4882a593Smuzhiyun #define RESET_VID_LOCK 231 158*4882a593Smuzhiyun #define RESET_A9_DMC_PIPEL 232 159*4882a593Smuzhiyun /* 233-255 */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #endif 162