1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* RESET0 */ 12*4882a593Smuzhiyun #define RESET_HIU 0 13*4882a593Smuzhiyun /* 1 */ 14*4882a593Smuzhiyun #define RESET_DOS 2 15*4882a593Smuzhiyun /* 3-4 */ 16*4882a593Smuzhiyun #define RESET_VIU 5 17*4882a593Smuzhiyun #define RESET_AFIFO 6 18*4882a593Smuzhiyun #define RESET_VID_PLL_DIV 7 19*4882a593Smuzhiyun /* 8-9 */ 20*4882a593Smuzhiyun #define RESET_VENC 10 21*4882a593Smuzhiyun #define RESET_ASSIST 11 22*4882a593Smuzhiyun #define RESET_PCIE_CTRL_A 12 23*4882a593Smuzhiyun #define RESET_VCBUS 13 24*4882a593Smuzhiyun #define RESET_PCIE_PHY 14 25*4882a593Smuzhiyun #define RESET_PCIE_APB 15 26*4882a593Smuzhiyun #define RESET_GIC 16 27*4882a593Smuzhiyun #define RESET_CAPB3_DECODE 17 28*4882a593Smuzhiyun /* 18 */ 29*4882a593Smuzhiyun #define RESET_HDMITX_CAPB3 19 30*4882a593Smuzhiyun #define RESET_DVALIN_CAPB3 20 31*4882a593Smuzhiyun #define RESET_DOS_CAPB3 21 32*4882a593Smuzhiyun /* 22 */ 33*4882a593Smuzhiyun #define RESET_CBUS_CAPB3 23 34*4882a593Smuzhiyun #define RESET_AHB_CNTL 24 35*4882a593Smuzhiyun #define RESET_AHB_DATA 25 36*4882a593Smuzhiyun #define RESET_VCBUS_CLK81 26 37*4882a593Smuzhiyun /* 27-31 */ 38*4882a593Smuzhiyun /* RESET1 */ 39*4882a593Smuzhiyun /* 32 */ 40*4882a593Smuzhiyun #define RESET_DEMUX 33 41*4882a593Smuzhiyun #define RESET_USB 34 42*4882a593Smuzhiyun #define RESET_DDR 35 43*4882a593Smuzhiyun /* 36 */ 44*4882a593Smuzhiyun #define RESET_BT656 37 45*4882a593Smuzhiyun #define RESET_AHB_SRAM 38 46*4882a593Smuzhiyun /* 39 */ 47*4882a593Smuzhiyun #define RESET_PARSER 40 48*4882a593Smuzhiyun /* 41 */ 49*4882a593Smuzhiyun #define RESET_ISA 42 50*4882a593Smuzhiyun #define RESET_ETHERNET 43 51*4882a593Smuzhiyun #define RESET_SD_EMMC_A 44 52*4882a593Smuzhiyun #define RESET_SD_EMMC_B 45 53*4882a593Smuzhiyun #define RESET_SD_EMMC_C 46 54*4882a593Smuzhiyun /* 47 */ 55*4882a593Smuzhiyun #define RESET_USB_PHY20 48 56*4882a593Smuzhiyun #define RESET_USB_PHY21 49 57*4882a593Smuzhiyun /* 50-60 */ 58*4882a593Smuzhiyun #define RESET_AUDIO_CODEC 61 59*4882a593Smuzhiyun /* 62-63 */ 60*4882a593Smuzhiyun /* RESET2 */ 61*4882a593Smuzhiyun /* 64 */ 62*4882a593Smuzhiyun #define RESET_AUDIO 65 63*4882a593Smuzhiyun #define RESET_HDMITX_PHY 66 64*4882a593Smuzhiyun /* 67 */ 65*4882a593Smuzhiyun #define RESET_MIPI_DSI_HOST 68 66*4882a593Smuzhiyun #define RESET_ALOCKER 69 67*4882a593Smuzhiyun #define RESET_GE2D 70 68*4882a593Smuzhiyun #define RESET_PARSER_REG 71 69*4882a593Smuzhiyun #define RESET_PARSER_FETCH 72 70*4882a593Smuzhiyun #define RESET_CTL 73 71*4882a593Smuzhiyun #define RESET_PARSER_TOP 74 72*4882a593Smuzhiyun /* 75-77 */ 73*4882a593Smuzhiyun #define RESET_DVALIN 78 74*4882a593Smuzhiyun #define RESET_HDMITX 79 75*4882a593Smuzhiyun /* 80-95 */ 76*4882a593Smuzhiyun /* RESET3 */ 77*4882a593Smuzhiyun /* 96-95 */ 78*4882a593Smuzhiyun #define RESET_DEMUX_TOP 105 79*4882a593Smuzhiyun #define RESET_DEMUX_DES_PL 106 80*4882a593Smuzhiyun #define RESET_DEMUX_S2P_0 107 81*4882a593Smuzhiyun #define RESET_DEMUX_S2P_1 108 82*4882a593Smuzhiyun #define RESET_DEMUX_0 109 83*4882a593Smuzhiyun #define RESET_DEMUX_1 110 84*4882a593Smuzhiyun #define RESET_DEMUX_2 111 85*4882a593Smuzhiyun /* 112-127 */ 86*4882a593Smuzhiyun /* RESET4 */ 87*4882a593Smuzhiyun /* 128-129 */ 88*4882a593Smuzhiyun #define RESET_MIPI_DSI_PHY 130 89*4882a593Smuzhiyun /* 131-132 */ 90*4882a593Smuzhiyun #define RESET_RDMA 133 91*4882a593Smuzhiyun #define RESET_VENCI 134 92*4882a593Smuzhiyun #define RESET_VENCP 135 93*4882a593Smuzhiyun /* 136 */ 94*4882a593Smuzhiyun #define RESET_VDAC 137 95*4882a593Smuzhiyun /* 138-139 */ 96*4882a593Smuzhiyun #define RESET_VDI6 140 97*4882a593Smuzhiyun #define RESET_VENCL 141 98*4882a593Smuzhiyun #define RESET_I2C_M1 142 99*4882a593Smuzhiyun #define RESET_I2C_M2 143 100*4882a593Smuzhiyun /* 144-159 */ 101*4882a593Smuzhiyun /* RESET5 */ 102*4882a593Smuzhiyun /* 160-191 */ 103*4882a593Smuzhiyun /* RESET6 */ 104*4882a593Smuzhiyun #define RESET_GEN 192 105*4882a593Smuzhiyun #define RESET_SPICC0 193 106*4882a593Smuzhiyun #define RESET_SC 194 107*4882a593Smuzhiyun #define RESET_SANA_3 195 108*4882a593Smuzhiyun #define RESET_I2C_M0 196 109*4882a593Smuzhiyun #define RESET_TS_PLL 197 110*4882a593Smuzhiyun #define RESET_SPICC1 198 111*4882a593Smuzhiyun #define RESET_STREAM 199 112*4882a593Smuzhiyun #define RESET_TS_CPU 200 113*4882a593Smuzhiyun #define RESET_UART0 201 114*4882a593Smuzhiyun #define RESET_UART1_2 202 115*4882a593Smuzhiyun #define RESET_ASYNC0 203 116*4882a593Smuzhiyun #define RESET_ASYNC1 204 117*4882a593Smuzhiyun #define RESET_SPIFC0 205 118*4882a593Smuzhiyun #define RESET_I2C_M3 206 119*4882a593Smuzhiyun /* 207-223 */ 120*4882a593Smuzhiyun /* RESET7 */ 121*4882a593Smuzhiyun #define RESET_USB_DDR_0 224 122*4882a593Smuzhiyun #define RESET_USB_DDR_1 225 123*4882a593Smuzhiyun #define RESET_USB_DDR_2 226 124*4882a593Smuzhiyun #define RESET_USB_DDR_3 227 125*4882a593Smuzhiyun #define RESET_TS_GPU 228 126*4882a593Smuzhiyun #define RESET_DEVICE_MMC_ARB 229 127*4882a593Smuzhiyun #define RESET_DVALIN_DMC_PIPL 230 128*4882a593Smuzhiyun #define RESET_VID_LOCK 231 129*4882a593Smuzhiyun #define RESET_NIC_DMC_PIPL 232 130*4882a593Smuzhiyun #define RESET_DMC_VPU_PIPL 233 131*4882a593Smuzhiyun #define RESET_GE2D_DMC_PIPL 234 132*4882a593Smuzhiyun #define RESET_HCODEC_DMC_PIPL 235 133*4882a593Smuzhiyun #define RESET_WAVE420_DMC_PIPL 236 134*4882a593Smuzhiyun #define RESET_HEVCF_DMC_PIPL 237 135*4882a593Smuzhiyun /* 238-255 */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif 138