1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (c) 2017 Amlogic, inc. 7*4882a593Smuzhiyun * Author: Yixun Lan <yixun.lan@amlogic.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H 12*4882a593Smuzhiyun #define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* RESET0 */ 15*4882a593Smuzhiyun #define RESET_HIU 0 16*4882a593Smuzhiyun #define RESET_PCIE_A 1 17*4882a593Smuzhiyun #define RESET_PCIE_B 2 18*4882a593Smuzhiyun #define RESET_DDR_TOP 3 19*4882a593Smuzhiyun /* 4 */ 20*4882a593Smuzhiyun #define RESET_VIU 5 21*4882a593Smuzhiyun #define RESET_PCIE_PHY 6 22*4882a593Smuzhiyun #define RESET_PCIE_APB 7 23*4882a593Smuzhiyun /* 8 */ 24*4882a593Smuzhiyun /* 9 */ 25*4882a593Smuzhiyun #define RESET_VENC 10 26*4882a593Smuzhiyun #define RESET_ASSIST 11 27*4882a593Smuzhiyun /* 12 */ 28*4882a593Smuzhiyun #define RESET_VCBUS 13 29*4882a593Smuzhiyun /* 14 */ 30*4882a593Smuzhiyun /* 15 */ 31*4882a593Smuzhiyun #define RESET_GIC 16 32*4882a593Smuzhiyun #define RESET_CAPB3_DECODE 17 33*4882a593Smuzhiyun /* 18-21 */ 34*4882a593Smuzhiyun #define RESET_SYS_CPU_CAPB3 22 35*4882a593Smuzhiyun #define RESET_CBUS_CAPB3 23 36*4882a593Smuzhiyun #define RESET_AHB_CNTL 24 37*4882a593Smuzhiyun #define RESET_AHB_DATA 25 38*4882a593Smuzhiyun #define RESET_VCBUS_CLK81 26 39*4882a593Smuzhiyun #define RESET_MMC 27 40*4882a593Smuzhiyun /* 28-31 */ 41*4882a593Smuzhiyun /* RESET1 */ 42*4882a593Smuzhiyun /* 32 */ 43*4882a593Smuzhiyun /* 33 */ 44*4882a593Smuzhiyun #define RESET_USB_OTG 34 45*4882a593Smuzhiyun #define RESET_DDR 35 46*4882a593Smuzhiyun #define RESET_AO_RESET 36 47*4882a593Smuzhiyun /* 37 */ 48*4882a593Smuzhiyun #define RESET_AHB_SRAM 38 49*4882a593Smuzhiyun /* 39 */ 50*4882a593Smuzhiyun /* 40 */ 51*4882a593Smuzhiyun #define RESET_DMA 41 52*4882a593Smuzhiyun #define RESET_ISA 42 53*4882a593Smuzhiyun #define RESET_ETHERNET 43 54*4882a593Smuzhiyun /* 44 */ 55*4882a593Smuzhiyun #define RESET_SD_EMMC_B 45 56*4882a593Smuzhiyun #define RESET_SD_EMMC_C 46 57*4882a593Smuzhiyun #define RESET_ROM_BOOT 47 58*4882a593Smuzhiyun #define RESET_SYS_CPU_0 48 59*4882a593Smuzhiyun #define RESET_SYS_CPU_1 49 60*4882a593Smuzhiyun #define RESET_SYS_CPU_2 50 61*4882a593Smuzhiyun #define RESET_SYS_CPU_3 51 62*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_0 52 63*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_1 53 64*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_2 54 65*4882a593Smuzhiyun #define RESET_SYS_CPU_CORE_3 55 66*4882a593Smuzhiyun #define RESET_SYS_PLL_DIV 56 67*4882a593Smuzhiyun #define RESET_SYS_CPU_AXI 57 68*4882a593Smuzhiyun #define RESET_SYS_CPU_L2 58 69*4882a593Smuzhiyun #define RESET_SYS_CPU_P 59 70*4882a593Smuzhiyun #define RESET_SYS_CPU_MBIST 60 71*4882a593Smuzhiyun /* 61-63 */ 72*4882a593Smuzhiyun /* RESET2 */ 73*4882a593Smuzhiyun /* 64 */ 74*4882a593Smuzhiyun /* 65 */ 75*4882a593Smuzhiyun #define RESET_AUDIO 66 76*4882a593Smuzhiyun /* 67 */ 77*4882a593Smuzhiyun #define RESET_MIPI_HOST 68 78*4882a593Smuzhiyun #define RESET_AUDIO_LOCKER 69 79*4882a593Smuzhiyun #define RESET_GE2D 70 80*4882a593Smuzhiyun /* 71-76 */ 81*4882a593Smuzhiyun #define RESET_AO_CPU_RESET 77 82*4882a593Smuzhiyun /* 78-95 */ 83*4882a593Smuzhiyun /* RESET3 */ 84*4882a593Smuzhiyun #define RESET_RING_OSCILLATOR 96 85*4882a593Smuzhiyun /* 97-127 */ 86*4882a593Smuzhiyun /* RESET4 */ 87*4882a593Smuzhiyun /* 128 */ 88*4882a593Smuzhiyun /* 129 */ 89*4882a593Smuzhiyun #define RESET_MIPI_PHY 130 90*4882a593Smuzhiyun /* 131-140 */ 91*4882a593Smuzhiyun #define RESET_VENCL 141 92*4882a593Smuzhiyun #define RESET_I2C_MASTER_2 142 93*4882a593Smuzhiyun #define RESET_I2C_MASTER_1 143 94*4882a593Smuzhiyun /* 144-159 */ 95*4882a593Smuzhiyun /* RESET5 */ 96*4882a593Smuzhiyun /* 160-191 */ 97*4882a593Smuzhiyun /* RESET6 */ 98*4882a593Smuzhiyun #define RESET_PERIPHS_GENERAL 192 99*4882a593Smuzhiyun #define RESET_PERIPHS_SPICC 193 100*4882a593Smuzhiyun /* 194 */ 101*4882a593Smuzhiyun /* 195 */ 102*4882a593Smuzhiyun #define RESET_PERIPHS_I2C_MASTER_0 196 103*4882a593Smuzhiyun /* 197-200 */ 104*4882a593Smuzhiyun #define RESET_PERIPHS_UART_0 201 105*4882a593Smuzhiyun #define RESET_PERIPHS_UART_1 202 106*4882a593Smuzhiyun /* 203-204 */ 107*4882a593Smuzhiyun #define RESET_PERIPHS_SPI_0 205 108*4882a593Smuzhiyun #define RESET_PERIPHS_I2C_MASTER_3 206 109*4882a593Smuzhiyun /* 207-223 */ 110*4882a593Smuzhiyun /* RESET7 */ 111*4882a593Smuzhiyun #define RESET_USB_DDR_0 224 112*4882a593Smuzhiyun #define RESET_USB_DDR_1 225 113*4882a593Smuzhiyun #define RESET_USB_DDR_2 226 114*4882a593Smuzhiyun #define RESET_USB_DDR_3 227 115*4882a593Smuzhiyun /* 228 */ 116*4882a593Smuzhiyun #define RESET_DEVICE_MMC_ARB 229 117*4882a593Smuzhiyun /* 230 */ 118*4882a593Smuzhiyun #define RESET_VID_LOCK 231 119*4882a593Smuzhiyun #define RESET_A9_DMC_PIPEL 232 120*4882a593Smuzhiyun #define RESET_DMC_VPU_PIPEL 233 121*4882a593Smuzhiyun /* 234-255 */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif 124