1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4*4882a593Smuzhiyun * Author: Xingyu Chen <xingyu.chen@amlogic.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* RESET0 */ 12*4882a593Smuzhiyun /* 0 */ 13*4882a593Smuzhiyun #define RESET_AM2AXI_VAD 1 14*4882a593Smuzhiyun /* 2-3 */ 15*4882a593Smuzhiyun #define RESET_PSRAM 4 16*4882a593Smuzhiyun #define RESET_PAD_CTRL 5 17*4882a593Smuzhiyun /* 6 */ 18*4882a593Smuzhiyun #define RESET_TEMP_SENSOR 7 19*4882a593Smuzhiyun #define RESET_AM2AXI_DEV 8 20*4882a593Smuzhiyun /* 9 */ 21*4882a593Smuzhiyun #define RESET_SPICC_A 10 22*4882a593Smuzhiyun #define RESET_MSR_CLK 11 23*4882a593Smuzhiyun #define RESET_AUDIO 12 24*4882a593Smuzhiyun #define RESET_ANALOG_CTRL 13 25*4882a593Smuzhiyun #define RESET_SAR_ADC 14 26*4882a593Smuzhiyun #define RESET_AUDIO_VAD 15 27*4882a593Smuzhiyun #define RESET_CEC 16 28*4882a593Smuzhiyun #define RESET_PWM_EF 17 29*4882a593Smuzhiyun #define RESET_PWM_CD 18 30*4882a593Smuzhiyun #define RESET_PWM_AB 19 31*4882a593Smuzhiyun /* 20 */ 32*4882a593Smuzhiyun #define RESET_IR_CTRL 21 33*4882a593Smuzhiyun #define RESET_I2C_S_A 22 34*4882a593Smuzhiyun /* 23 */ 35*4882a593Smuzhiyun #define RESET_I2C_M_D 24 36*4882a593Smuzhiyun #define RESET_I2C_M_C 25 37*4882a593Smuzhiyun #define RESET_I2C_M_B 26 38*4882a593Smuzhiyun #define RESET_I2C_M_A 27 39*4882a593Smuzhiyun #define RESET_I2C_PROD_AHB 28 40*4882a593Smuzhiyun #define RESET_I2C_PROD 29 41*4882a593Smuzhiyun /* 30-31 */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* RESET1 */ 44*4882a593Smuzhiyun #define RESET_ACODEC 32 45*4882a593Smuzhiyun #define RESET_DMA 33 46*4882a593Smuzhiyun #define RESET_SD_EMMC_A 34 47*4882a593Smuzhiyun /* 35 */ 48*4882a593Smuzhiyun #define RESET_USBCTRL 36 49*4882a593Smuzhiyun /* 37 */ 50*4882a593Smuzhiyun #define RESET_USBPHY 38 51*4882a593Smuzhiyun /* 39-41 */ 52*4882a593Smuzhiyun #define RESET_RSA 42 53*4882a593Smuzhiyun #define RESET_DMC 43 54*4882a593Smuzhiyun /* 44 */ 55*4882a593Smuzhiyun #define RESET_IRQ_CTRL 45 56*4882a593Smuzhiyun /* 46 */ 57*4882a593Smuzhiyun #define RESET_NIC_VAD 47 58*4882a593Smuzhiyun #define RESET_NIC_AXI 48 59*4882a593Smuzhiyun #define RESET_RAMA 49 60*4882a593Smuzhiyun #define RESET_RAMB 50 61*4882a593Smuzhiyun /* 51-52 */ 62*4882a593Smuzhiyun #define RESET_ROM 53 63*4882a593Smuzhiyun #define RESET_SPIFC 54 64*4882a593Smuzhiyun #define RESET_GIC 55 65*4882a593Smuzhiyun #define RESET_UART_C 56 66*4882a593Smuzhiyun #define RESET_UART_B 57 67*4882a593Smuzhiyun #define RESET_UART_A 58 68*4882a593Smuzhiyun #define RESET_OSC_RING 59 69*4882a593Smuzhiyun /* 60-63 */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* RESET2 */ 72*4882a593Smuzhiyun /* 64-95 */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75