1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Intel Corporation. All rights reserved 4*4882a593Smuzhiyun * Copyright (C) 2016 Altera Corporation. All rights reserved 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* MPUMODRST */ 13*4882a593Smuzhiyun #define CPU0_RESET 0 14*4882a593Smuzhiyun #define CPU1_RESET 1 15*4882a593Smuzhiyun #define CPU2_RESET 2 16*4882a593Smuzhiyun #define CPU3_RESET 3 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* PER0MODRST */ 19*4882a593Smuzhiyun #define EMAC0_RESET 32 20*4882a593Smuzhiyun #define EMAC1_RESET 33 21*4882a593Smuzhiyun #define EMAC2_RESET 34 22*4882a593Smuzhiyun #define USB0_RESET 35 23*4882a593Smuzhiyun #define USB1_RESET 36 24*4882a593Smuzhiyun #define NAND_RESET 37 25*4882a593Smuzhiyun /* 38 is empty */ 26*4882a593Smuzhiyun #define SDMMC_RESET 39 27*4882a593Smuzhiyun #define EMAC0_OCP_RESET 40 28*4882a593Smuzhiyun #define EMAC1_OCP_RESET 41 29*4882a593Smuzhiyun #define EMAC2_OCP_RESET 42 30*4882a593Smuzhiyun #define USB0_OCP_RESET 43 31*4882a593Smuzhiyun #define USB1_OCP_RESET 44 32*4882a593Smuzhiyun #define NAND_OCP_RESET 45 33*4882a593Smuzhiyun /* 46 is empty */ 34*4882a593Smuzhiyun #define SDMMC_OCP_RESET 47 35*4882a593Smuzhiyun #define DMA_RESET 48 36*4882a593Smuzhiyun #define SPIM0_RESET 49 37*4882a593Smuzhiyun #define SPIM1_RESET 50 38*4882a593Smuzhiyun #define SPIS0_RESET 51 39*4882a593Smuzhiyun #define SPIS1_RESET 52 40*4882a593Smuzhiyun #define DMA_OCP_RESET 53 41*4882a593Smuzhiyun #define EMAC_PTP_RESET 54 42*4882a593Smuzhiyun /* 55 is empty*/ 43*4882a593Smuzhiyun #define DMAIF0_RESET 56 44*4882a593Smuzhiyun #define DMAIF1_RESET 57 45*4882a593Smuzhiyun #define DMAIF2_RESET 58 46*4882a593Smuzhiyun #define DMAIF3_RESET 59 47*4882a593Smuzhiyun #define DMAIF4_RESET 60 48*4882a593Smuzhiyun #define DMAIF5_RESET 61 49*4882a593Smuzhiyun #define DMAIF6_RESET 62 50*4882a593Smuzhiyun #define DMAIF7_RESET 63 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* PER1MODRST */ 53*4882a593Smuzhiyun #define WATCHDOG0_RESET 64 54*4882a593Smuzhiyun #define WATCHDOG1_RESET 65 55*4882a593Smuzhiyun #define WATCHDOG2_RESET 66 56*4882a593Smuzhiyun #define WATCHDOG3_RESET 67 57*4882a593Smuzhiyun #define L4SYSTIMER0_RESET 68 58*4882a593Smuzhiyun #define L4SYSTIMER1_RESET 69 59*4882a593Smuzhiyun #define SPTIMER0_RESET 70 60*4882a593Smuzhiyun #define SPTIMER1_RESET 71 61*4882a593Smuzhiyun #define I2C0_RESET 72 62*4882a593Smuzhiyun #define I2C1_RESET 73 63*4882a593Smuzhiyun #define I2C2_RESET 74 64*4882a593Smuzhiyun #define I2C3_RESET 75 65*4882a593Smuzhiyun #define I2C4_RESET 76 66*4882a593Smuzhiyun /* 77-79 is empty */ 67*4882a593Smuzhiyun #define UART0_RESET 80 68*4882a593Smuzhiyun #define UART1_RESET 81 69*4882a593Smuzhiyun /* 82-87 is empty */ 70*4882a593Smuzhiyun #define GPIO0_RESET 88 71*4882a593Smuzhiyun #define GPIO1_RESET 89 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* BRGMODRST */ 74*4882a593Smuzhiyun #define SOC2FPGA_RESET 96 75*4882a593Smuzhiyun #define LWHPS2FPGA_RESET 97 76*4882a593Smuzhiyun #define FPGA2SOC_RESET 98 77*4882a593Smuzhiyun #define F2SSDRAM0_RESET 99 78*4882a593Smuzhiyun #define F2SSDRAM1_RESET 100 79*4882a593Smuzhiyun #define F2SSDRAM2_RESET 101 80*4882a593Smuzhiyun #define DDRSCH_RESET 102 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* COLDMODRST */ 83*4882a593Smuzhiyun #define CPUPO0_RESET 160 84*4882a593Smuzhiyun #define CPUPO1_RESET 161 85*4882a593Smuzhiyun #define CPUPO2_RESET 162 86*4882a593Smuzhiyun #define CPUPO3_RESET 163 87*4882a593Smuzhiyun /* 164-167 is empty */ 88*4882a593Smuzhiyun #define L2_RESET 168 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* DBGMODRST */ 91*4882a593Smuzhiyun #define DBG_RESET 224 92*4882a593Smuzhiyun #define CSDAP_RESET 225 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* TAPMODRST */ 95*4882a593Smuzhiyun #define TAP_RESET 256 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif 98