1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright Intel Corporation (C) 2017. All Rights Reserved 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Adapted from altr,rst-mgr-a10.h 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H 11*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Peripheral PHY resets */ 14*4882a593Smuzhiyun #define A10SR_RESET_ENET_HPS 0 15*4882a593Smuzhiyun #define A10SR_RESET_PCIE 1 16*4882a593Smuzhiyun #define A10SR_RESET_FILE 2 17*4882a593Smuzhiyun #define A10SR_RESET_BQSPI 3 18*4882a593Smuzhiyun #define A10SR_RESET_USB 4 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define A10SR_RESET_NUM 5 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif 23