1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* MPUMODRST */ 10*4882a593Smuzhiyun #define CPU0_RESET 0 11*4882a593Smuzhiyun #define CPU1_RESET 1 12*4882a593Smuzhiyun #define WDS_RESET 2 13*4882a593Smuzhiyun #define SCUPER_RESET 3 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* PER0MODRST */ 16*4882a593Smuzhiyun #define EMAC0_RESET 32 17*4882a593Smuzhiyun #define EMAC1_RESET 33 18*4882a593Smuzhiyun #define EMAC2_RESET 34 19*4882a593Smuzhiyun #define USB0_RESET 35 20*4882a593Smuzhiyun #define USB1_RESET 36 21*4882a593Smuzhiyun #define NAND_RESET 37 22*4882a593Smuzhiyun #define QSPI_RESET 38 23*4882a593Smuzhiyun #define SDMMC_RESET 39 24*4882a593Smuzhiyun #define EMAC0_OCP_RESET 40 25*4882a593Smuzhiyun #define EMAC1_OCP_RESET 41 26*4882a593Smuzhiyun #define EMAC2_OCP_RESET 42 27*4882a593Smuzhiyun #define USB0_OCP_RESET 43 28*4882a593Smuzhiyun #define USB1_OCP_RESET 44 29*4882a593Smuzhiyun #define NAND_OCP_RESET 45 30*4882a593Smuzhiyun #define QSPI_OCP_RESET 46 31*4882a593Smuzhiyun #define SDMMC_OCP_RESET 47 32*4882a593Smuzhiyun #define DMA_RESET 48 33*4882a593Smuzhiyun #define SPIM0_RESET 49 34*4882a593Smuzhiyun #define SPIM1_RESET 50 35*4882a593Smuzhiyun #define SPIS0_RESET 51 36*4882a593Smuzhiyun #define SPIS1_RESET 52 37*4882a593Smuzhiyun #define DMA_OCP_RESET 53 38*4882a593Smuzhiyun #define EMAC_PTP_RESET 54 39*4882a593Smuzhiyun /* 55 is empty*/ 40*4882a593Smuzhiyun #define DMAIF0_RESET 56 41*4882a593Smuzhiyun #define DMAIF1_RESET 57 42*4882a593Smuzhiyun #define DMAIF2_RESET 58 43*4882a593Smuzhiyun #define DMAIF3_RESET 59 44*4882a593Smuzhiyun #define DMAIF4_RESET 60 45*4882a593Smuzhiyun #define DMAIF5_RESET 61 46*4882a593Smuzhiyun #define DMAIF6_RESET 62 47*4882a593Smuzhiyun #define DMAIF7_RESET 63 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* PER1MODRST */ 50*4882a593Smuzhiyun #define L4WD0_RESET 64 51*4882a593Smuzhiyun #define L4WD1_RESET 65 52*4882a593Smuzhiyun #define L4SYSTIMER0_RESET 66 53*4882a593Smuzhiyun #define L4SYSTIMER1_RESET 67 54*4882a593Smuzhiyun #define SPTIMER0_RESET 68 55*4882a593Smuzhiyun #define SPTIMER1_RESET 69 56*4882a593Smuzhiyun /* 70-71 is reserved */ 57*4882a593Smuzhiyun #define I2C0_RESET 72 58*4882a593Smuzhiyun #define I2C1_RESET 73 59*4882a593Smuzhiyun #define I2C2_RESET 74 60*4882a593Smuzhiyun #define I2C3_RESET 75 61*4882a593Smuzhiyun #define I2C4_RESET 76 62*4882a593Smuzhiyun /* 77-79 is reserved */ 63*4882a593Smuzhiyun #define UART0_RESET 80 64*4882a593Smuzhiyun #define UART1_RESET 81 65*4882a593Smuzhiyun /* 82-87 is reserved */ 66*4882a593Smuzhiyun #define GPIO0_RESET 88 67*4882a593Smuzhiyun #define GPIO1_RESET 89 68*4882a593Smuzhiyun #define GPIO2_RESET 90 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* BRGMODRST */ 71*4882a593Smuzhiyun #define HPS2FPGA_RESET 96 72*4882a593Smuzhiyun #define LWHPS2FPGA_RESET 97 73*4882a593Smuzhiyun #define FPGA2HPS_RESET 98 74*4882a593Smuzhiyun #define F2SSDRAM0_RESET 99 75*4882a593Smuzhiyun #define F2SSDRAM1_RESET 100 76*4882a593Smuzhiyun #define F2SSDRAM2_RESET 101 77*4882a593Smuzhiyun #define DDRSCH_RESET 102 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* SYSMODRST*/ 80*4882a593Smuzhiyun #define ROM_RESET 128 81*4882a593Smuzhiyun #define OCRAM_RESET 129 82*4882a593Smuzhiyun /* 130 is reserved */ 83*4882a593Smuzhiyun #define FPGAMGR_RESET 131 84*4882a593Smuzhiyun #define S2F_RESET 132 85*4882a593Smuzhiyun #define SYSDBG_RESET 133 86*4882a593Smuzhiyun #define OCRAM_OCP_RESET 134 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* COLDMODRST */ 89*4882a593Smuzhiyun #define CLKMGRCOLD_RESET 160 90*4882a593Smuzhiyun /* 161-162 is reserved */ 91*4882a593Smuzhiyun #define S2FCOLD_RESET 163 92*4882a593Smuzhiyun #define TIMESTAMPCOLD_RESET 164 93*4882a593Smuzhiyun #define TAPCOLD_RESET 165 94*4882a593Smuzhiyun #define HMCCOLD_RESET 166 95*4882a593Smuzhiyun #define IOMGRCOLD_RESET 167 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* NRSTMODRST */ 98*4882a593Smuzhiyun #define NRSTPINOE_RESET 192 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* DBGMODRST */ 101*4882a593Smuzhiyun #define DBG_RESET 224 102*4882a593Smuzhiyun #endif 103