1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* MPUMODRST */ 10*4882a593Smuzhiyun #define CPU0_RESET 0 11*4882a593Smuzhiyun #define CPU1_RESET 1 12*4882a593Smuzhiyun #define WDS_RESET 2 13*4882a593Smuzhiyun #define SCUPER_RESET 3 14*4882a593Smuzhiyun #define L2_RESET 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* PERMODRST */ 17*4882a593Smuzhiyun #define EMAC0_RESET 32 18*4882a593Smuzhiyun #define EMAC1_RESET 33 19*4882a593Smuzhiyun #define USB0_RESET 34 20*4882a593Smuzhiyun #define USB1_RESET 35 21*4882a593Smuzhiyun #define NAND_RESET 36 22*4882a593Smuzhiyun #define QSPI_RESET 37 23*4882a593Smuzhiyun #define L4WD0_RESET 38 24*4882a593Smuzhiyun #define L4WD1_RESET 39 25*4882a593Smuzhiyun #define OSC1TIMER0_RESET 40 26*4882a593Smuzhiyun #define OSC1TIMER1_RESET 41 27*4882a593Smuzhiyun #define SPTIMER0_RESET 42 28*4882a593Smuzhiyun #define SPTIMER1_RESET 43 29*4882a593Smuzhiyun #define I2C0_RESET 44 30*4882a593Smuzhiyun #define I2C1_RESET 45 31*4882a593Smuzhiyun #define I2C2_RESET 46 32*4882a593Smuzhiyun #define I2C3_RESET 47 33*4882a593Smuzhiyun #define UART0_RESET 48 34*4882a593Smuzhiyun #define UART1_RESET 49 35*4882a593Smuzhiyun #define SPIM0_RESET 50 36*4882a593Smuzhiyun #define SPIM1_RESET 51 37*4882a593Smuzhiyun #define SPIS0_RESET 52 38*4882a593Smuzhiyun #define SPIS1_RESET 53 39*4882a593Smuzhiyun #define SDMMC_RESET 54 40*4882a593Smuzhiyun #define CAN0_RESET 55 41*4882a593Smuzhiyun #define CAN1_RESET 56 42*4882a593Smuzhiyun #define GPIO0_RESET 57 43*4882a593Smuzhiyun #define GPIO1_RESET 58 44*4882a593Smuzhiyun #define GPIO2_RESET 59 45*4882a593Smuzhiyun #define DMA_RESET 60 46*4882a593Smuzhiyun #define SDR_RESET 61 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* PER2MODRST */ 49*4882a593Smuzhiyun #define DMAIF0_RESET 64 50*4882a593Smuzhiyun #define DMAIF1_RESET 65 51*4882a593Smuzhiyun #define DMAIF2_RESET 66 52*4882a593Smuzhiyun #define DMAIF3_RESET 67 53*4882a593Smuzhiyun #define DMAIF4_RESET 68 54*4882a593Smuzhiyun #define DMAIF5_RESET 69 55*4882a593Smuzhiyun #define DMAIF6_RESET 70 56*4882a593Smuzhiyun #define DMAIF7_RESET 71 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* BRGMODRST */ 59*4882a593Smuzhiyun #define HPS2FPGA_RESET 96 60*4882a593Smuzhiyun #define LWHPS2FPGA_RESET 97 61*4882a593Smuzhiyun #define FPGA2HPS_RESET 98 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* MISCMODRST*/ 64*4882a593Smuzhiyun #define ROM_RESET 128 65*4882a593Smuzhiyun #define OCRAM_RESET 129 66*4882a593Smuzhiyun #define SYSMGR_RESET 130 67*4882a593Smuzhiyun #define SYSMGRCOLD_RESET 131 68*4882a593Smuzhiyun #define FPGAMGR_RESET 132 69*4882a593Smuzhiyun #define ACPIDMAP_RESET 133 70*4882a593Smuzhiyun #define S2F_RESET 134 71*4882a593Smuzhiyun #define S2FCOLD_RESET 135 72*4882a593Smuzhiyun #define NRSTPIN_RESET 136 73*4882a593Smuzhiyun #define TIMESTAMPCOLD_RESET 137 74*4882a593Smuzhiyun #define CLKMGRCOLD_RESET 138 75*4882a593Smuzhiyun #define SCANMGR_RESET 139 76*4882a593Smuzhiyun #define FRZCTRLCOLD_RESET 140 77*4882a593Smuzhiyun #define SYSDBG_RESET 141 78*4882a593Smuzhiyun #define DBG_RESET 142 79*4882a593Smuzhiyun #define TAPCOLD_RESET 143 80*4882a593Smuzhiyun #define SDRCOLD_RESET 144 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83