1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree binding constants for Actions Semi S500 Reset Management Unit 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014 Actions Semi Inc. 6*4882a593Smuzhiyun * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_ACTIONS_S500_RESET_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define RESET_DMAC 0 13*4882a593Smuzhiyun #define RESET_NORIF 1 14*4882a593Smuzhiyun #define RESET_DDR 2 15*4882a593Smuzhiyun #define RESET_NANDC 3 16*4882a593Smuzhiyun #define RESET_SD0 4 17*4882a593Smuzhiyun #define RESET_SD1 5 18*4882a593Smuzhiyun #define RESET_PCM1 6 19*4882a593Smuzhiyun #define RESET_DE 7 20*4882a593Smuzhiyun #define RESET_LCD 8 21*4882a593Smuzhiyun #define RESET_SD2 9 22*4882a593Smuzhiyun #define RESET_DSI 10 23*4882a593Smuzhiyun #define RESET_CSI 11 24*4882a593Smuzhiyun #define RESET_BISP 12 25*4882a593Smuzhiyun #define RESET_KEY 13 26*4882a593Smuzhiyun #define RESET_GPIO 14 27*4882a593Smuzhiyun #define RESET_AUDIO 15 28*4882a593Smuzhiyun #define RESET_PCM0 16 29*4882a593Smuzhiyun #define RESET_VDE 17 30*4882a593Smuzhiyun #define RESET_VCE 18 31*4882a593Smuzhiyun #define RESET_GPU3D 19 32*4882a593Smuzhiyun #define RESET_NIC301 20 33*4882a593Smuzhiyun #define RESET_LENS 21 34*4882a593Smuzhiyun #define RESET_PERIPHRESET 22 35*4882a593Smuzhiyun #define RESET_USB2_0 23 36*4882a593Smuzhiyun #define RESET_TVOUT 24 37*4882a593Smuzhiyun #define RESET_HDMI 25 38*4882a593Smuzhiyun #define RESET_HDCP2TX 26 39*4882a593Smuzhiyun #define RESET_UART6 27 40*4882a593Smuzhiyun #define RESET_UART0 28 41*4882a593Smuzhiyun #define RESET_UART1 29 42*4882a593Smuzhiyun #define RESET_UART2 30 43*4882a593Smuzhiyun #define RESET_SPI0 31 44*4882a593Smuzhiyun #define RESET_SPI1 32 45*4882a593Smuzhiyun #define RESET_SPI2 33 46*4882a593Smuzhiyun #define RESET_SPI3 34 47*4882a593Smuzhiyun #define RESET_I2C0 35 48*4882a593Smuzhiyun #define RESET_I2C1 36 49*4882a593Smuzhiyun #define RESET_USB3 37 50*4882a593Smuzhiyun #define RESET_UART3 38 51*4882a593Smuzhiyun #define RESET_UART4 39 52*4882a593Smuzhiyun #define RESET_UART5 40 53*4882a593Smuzhiyun #define RESET_I2C2 41 54*4882a593Smuzhiyun #define RESET_I2C3 42 55*4882a593Smuzhiyun #define RESET_ETHERNET 43 56*4882a593Smuzhiyun #define RESET_CHIPID 44 57*4882a593Smuzhiyun #define RESET_USB2_1 45 58*4882a593Smuzhiyun #define RESET_WD0RESET 46 59*4882a593Smuzhiyun #define RESET_WD1RESET 47 60*4882a593Smuzhiyun #define RESET_WD2RESET 48 61*4882a593Smuzhiyun #define RESET_WD3RESET 49 62*4882a593Smuzhiyun #define RESET_DBG0RESET 50 63*4882a593Smuzhiyun #define RESET_DBG1RESET 51 64*4882a593Smuzhiyun #define RESET_DBG2RESET 52 65*4882a593Smuzhiyun #define RESET_DBG3RESET 53 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */ 68