1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2*4882a593Smuzhiyun // 3*4882a593Smuzhiyun // Device Tree binding constants for Actions Semi S900 Reset Management Unit 4*4882a593Smuzhiyun // 5*4882a593Smuzhiyun // Copyright (c) 2018 Linaro Ltd. 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H 8*4882a593Smuzhiyun #define __DT_BINDINGS_ACTIONS_S900_RESET_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define RESET_CHIPID 0 11*4882a593Smuzhiyun #define RESET_CPU_SCNT 1 12*4882a593Smuzhiyun #define RESET_SRAMI 2 13*4882a593Smuzhiyun #define RESET_DDR_CTL_PHY 3 14*4882a593Smuzhiyun #define RESET_DMAC 4 15*4882a593Smuzhiyun #define RESET_GPIO 5 16*4882a593Smuzhiyun #define RESET_BISP_AXI 6 17*4882a593Smuzhiyun #define RESET_CSI0 7 18*4882a593Smuzhiyun #define RESET_CSI1 8 19*4882a593Smuzhiyun #define RESET_DE 9 20*4882a593Smuzhiyun #define RESET_DSI 10 21*4882a593Smuzhiyun #define RESET_GPU3D_PA 11 22*4882a593Smuzhiyun #define RESET_GPU3D_PB 12 23*4882a593Smuzhiyun #define RESET_HDE 13 24*4882a593Smuzhiyun #define RESET_I2C0 14 25*4882a593Smuzhiyun #define RESET_I2C1 15 26*4882a593Smuzhiyun #define RESET_I2C2 16 27*4882a593Smuzhiyun #define RESET_I2C3 17 28*4882a593Smuzhiyun #define RESET_I2C4 18 29*4882a593Smuzhiyun #define RESET_I2C5 19 30*4882a593Smuzhiyun #define RESET_IMX 20 31*4882a593Smuzhiyun #define RESET_NANDC0 21 32*4882a593Smuzhiyun #define RESET_NANDC1 22 33*4882a593Smuzhiyun #define RESET_SD0 23 34*4882a593Smuzhiyun #define RESET_SD1 24 35*4882a593Smuzhiyun #define RESET_SD2 25 36*4882a593Smuzhiyun #define RESET_SD3 26 37*4882a593Smuzhiyun #define RESET_SPI0 27 38*4882a593Smuzhiyun #define RESET_SPI1 28 39*4882a593Smuzhiyun #define RESET_SPI2 29 40*4882a593Smuzhiyun #define RESET_SPI3 30 41*4882a593Smuzhiyun #define RESET_UART0 31 42*4882a593Smuzhiyun #define RESET_UART1 32 43*4882a593Smuzhiyun #define RESET_UART2 33 44*4882a593Smuzhiyun #define RESET_UART3 34 45*4882a593Smuzhiyun #define RESET_UART4 35 46*4882a593Smuzhiyun #define RESET_UART5 36 47*4882a593Smuzhiyun #define RESET_UART6 37 48*4882a593Smuzhiyun #define RESET_HDMI 38 49*4882a593Smuzhiyun #define RESET_LVDS 39 50*4882a593Smuzhiyun #define RESET_EDP 40 51*4882a593Smuzhiyun #define RESET_USB2HUB 41 52*4882a593Smuzhiyun #define RESET_USB2HSIC 42 53*4882a593Smuzhiyun #define RESET_USB3 43 54*4882a593Smuzhiyun #define RESET_PCM1 44 55*4882a593Smuzhiyun #define RESET_AUDIO 45 56*4882a593Smuzhiyun #define RESET_PCM0 46 57*4882a593Smuzhiyun #define RESET_SE 47 58*4882a593Smuzhiyun #define RESET_GIC 48 59*4882a593Smuzhiyun #define RESET_DDR_CTL_PHY_AXI 49 60*4882a593Smuzhiyun #define RESET_CMU_DDR 50 61*4882a593Smuzhiyun #define RESET_DMM 51 62*4882a593Smuzhiyun #define RESET_HDCP2TX 52 63*4882a593Smuzhiyun #define RESET_ETHERNET 53 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ 66