1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Yong Liang <yong.liang@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183 8*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_MT8183 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* INFRACFG AO resets */ 11*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_THERM_SW_RST 0 12*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1 13*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3 14*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MSDC3_SW_RST 4 15*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MSDC2_SW_RST 5 16*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MSDC1_SW_RST 6 17*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MSDC0_SW_RST 7 18*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_APDMA_SW_RST 9 19*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10 20*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_BTIF_SW_RST 12 21*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14 22*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_AUXADC_SW_RST 15 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_IRTX_SW_RST 32 25*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPI0_SW_RST 33 26*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C0_SW_RST 34 27*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C1_SW_RST 35 28*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C2_SW_RST 36 29*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C3_SW_RST 37 30*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UART0_SW_RST 38 31*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UART1_SW_RST 39 32*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UART2_SW_RST 40 33*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_PWM_SW_RST 41 34*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPI1_SW_RST 42 35*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C4_SW_RST 43 36*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_DVFSP_SW_RST 44 37*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPI2_SW_RST 45 38*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPI3_SW_RST 46 39*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64 42*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPM_SW_RST 65 43*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_USBSIF_SW_RST 66 44*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_KP_SW_RST 68 45*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_APXGPT_SW_RST 69 46*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70 47*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 48*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_DX_CC_SW_RST 72 49*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96 52*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_GCE_SW_RST 97 53*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_CLDMA_SW_RST 98 54*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_TRNG_SW_RST 99 55*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 56*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 57*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105 58*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106 59*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107 60*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108 61*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C5_SW_RST 109 62*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110 63*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111 64*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPI4_SW_RST 112 65*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_SPI5_SW_RST 113 66*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 67*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 68*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 69*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117 70*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 71*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 72*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C6_SW_RST 120 73*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121 74*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122 75*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 76*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 77*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 78*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 79*4882a593Smuzhiyun #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define MT8183_INFRACFG_SW_RST_NUM 128 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define MT8183_TOPRGU_MM_SW_RST 1 84*4882a593Smuzhiyun #define MT8183_TOPRGU_MFG_SW_RST 2 85*4882a593Smuzhiyun #define MT8183_TOPRGU_VENC_SW_RST 3 86*4882a593Smuzhiyun #define MT8183_TOPRGU_VDEC_SW_RST 4 87*4882a593Smuzhiyun #define MT8183_TOPRGU_IMG_SW_RST 5 88*4882a593Smuzhiyun #define MT8183_TOPRGU_MD_SW_RST 7 89*4882a593Smuzhiyun #define MT8183_TOPRGU_CONN_SW_RST 9 90*4882a593Smuzhiyun #define MT8183_TOPRGU_CONN_MCU_SW_RST 12 91*4882a593Smuzhiyun #define MT8183_TOPRGU_IPU0_SW_RST 14 92*4882a593Smuzhiyun #define MT8183_TOPRGU_IPU1_SW_RST 15 93*4882a593Smuzhiyun #define MT8183_TOPRGU_AUDIO_SW_RST 17 94*4882a593Smuzhiyun #define MT8183_TOPRGU_CAMSYS_SW_RST 18 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define MT8183_TOPRGU_SW_RST_NUM 19 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ 99